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Design and Fabrication of Second-Order Multibit Sigma-Delta Modulator  

김선홍 (전북대학 전기공학과)
최석우 (전북대학 전자정보공학)
조성익 (전북대학 전자정보공학)
김동용 (전북대학 전자정보공학부)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers D / v.53, no.9, 2004 , pp. 650-656 More about this Journal
Abstract
This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.
Keywords
Sigma-Delta Modulator; Data Weighted Averaging; Multibit; Noise-Shaping;
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