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The Third-Order Multibit Sigma-Delta Modulator with Data Weighted Averaging  

김선홍 (전북대학교 전기공학과)
최석우 (전북대학교 전자정보공학부)
조성익 (전북대학교 전자정보공학부)
김동용 (전북대학교 전저정보공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.9, 2004 , pp. 107-114 More about this Journal
Abstract
This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.
Keywords
sigma-delta modulator; data weighted averaging; multibit; noise-shaping.;
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