• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.2
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• pp.89-92
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• 2010

A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.387-391
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• 2011

A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.121-126
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• 2000

In the fast sampling limit the delta operator model tends to the analog system model. This fundamental property of the delta operator model unifies continuous and discrete time control system. In this paper we study robust linear optimal model following servo system in the presence of disturbances and parameter perturbations. A technique to directly design the generalized differential operator based unified control system that covers both differential operator based continuous time and delta operator based discrete time case is presented. The quadratic criterion function for a linear system is used to design the robust unified servo control system The characteristics of the proposed servo system are analysed and simulated to verify the robustness.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.6
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• pp.747-752
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• 1999

In the fast sampling limit, the delta operator model tends to the analog system model. This fundamental property of the delta operator model unifies continuous and discrete time control system. In this paper, we study robust linear optimal model following servo system in the presence of disturbances and parameter perturbations. A technique to directly design the generalized differential operator based unified control system that convers both differential operator based continuous time and delta operator based discrete time case is presented. The quadratic criterion function for a linear system is used to design the robust unified servo control. The characteristics of the proposed servo system are analysed and simulated to verify the robustness.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.107-114
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• 2004

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.156-159
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• 2000

This paper presents a low-voltage, low-power $\Sigma$Δ modulator for audio applications. It use a simple second-order fully-differential switched-capacitor structure with a sampling frequency of 12.5 MHz and oversampling ratio of 256. It operates from a single 1.5V Bower supply and dissipates 2 ㎽. Extensive simulations using 0.25 ${\mu}{\textrm}{m}$ CMOS Process parameters show that it achieves 96㏈ peak SNDR in a 22 KHz bandwidth.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.73-83
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• 1984

The performances of embedded adaptive differential pulse code modulation (ADPCM), embedded adaptive delta modulation (ADM), and the same systems with a delayedfecision scheme have been studied with real speech over a wide dynamic range. The embedded ADPCM and ADM coders have been obtained by modifying the conventional ADPCM and ADM coders. The basic scheme of the embedded ADPCM coder is based on the ADPCM originally proposed by Cummiskey et at. For embedded ADM systems, we have modified continuously variable slope DM (CVSD) and hybrid commanding DM (HCDM) systems. Among these embedded coders, the performance of the embedded HCDM is superior to the other coders over a wide range of transmission rate from 16 to 64 kbits/s, When the delayedtecision scheme is applied to the embedded ADPCM the performance is improved significantly at all transmission rates. But, in the embedded ADM systems with 16 kHz sampling rate, the performance improvement resulting from delayed decision is not drastic as is in the embedded ADPCM with the same number of delayed samples.