• 문화기술의 융합
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• 제5권4호
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• pp.349-354
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• 2019

건설현장에서 추락으로 인해 사망하는 근로자는 전체 사망자의 약 40%를 차지하며 사망사고 주요 발생 형태로 나타나고 있다, 또한 우리나라 인구구성이 점차 고령화됨에 따라 건설현장에서도 고령화 비율이 점점 높아지고 있으며 신체기능 저하 인지능력 저하 등에 따른 추락재해가 점점 증가추세에 있다. 이에 따라 고령 근로자 추락에 미치는 요인에 대하여 설문조사를 실시하였으며 재해 당사자인 고령 근로자에 초점을 맞춰 보다 근본적인 추락 예방대책을 제시하고자 한다.

• Design & Manufacturing
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• 제15권3호
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• pp.26-31
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• 2021

In this study, laser-induced periodic surface structure (LIPSS) was fabricated on Ni, Si, and GaAs samples using a flat-top beam with a uniform energy distribution that was fabricated using a Gaussian femtosecond laser with a mechanical slit and tube lens. Unlike the Gaussian beam, the flat-top beam has a uniform beam profile, therefore the center and the periphery of the fabricated LIPSS have similar line periodicity. In addition, LIPSS was obtained not only in metals but also in metalloids and metals and metalloid compounds by using the narrow pulse width characteristic of a femtosecond laser.

• Design & Manufacturing
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• 제16권1호
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• pp.1-8
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• 2022

The importance of fast and accurate body temperature measurement with a portable thermometer is increasing. In order to reduce the temperature measurement response time of the infrared ear thermometer, it is very important to develop a structure for a thermometer having an efficient heat transfer path. Most of the existing ear thermometers are single structures that do not consider thermal efficiency, which may delay measurement time and reduce measurement accuracy. Therefore, in this study, the upper part of the thermometer in contact with the ear is made of a thermally conductive material, and the lower part of the thermometer is made of a thermal barrier material so that heat can be concentrated on the infrared sensor of the thermometer by blocking the upper part of the heat. For the efficiency of production, it was intended to be manufactured through the double injection process, and for this purpose, in this paper, the optimal process parameters were derived through the double injection process analysis.

• 한국기계가공학회지
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• 제21권9호
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• pp.1-11
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• 2022

Recently, there has been continuous technological development in the semiconductor industry, and semiconductor manufacturing technologies are being advanced and highly integrated. For this reason, ceramic material having excellent heat resistance, wear resistance, and conductivity are used as components in semiconductor manufacturing. Among them, the probe card's space transformer is used as ceramic material to prevent electronic signal noise during the electrical die sorting of semiconductor function testing. However, implementing a bulk-type space transformer with a thickness of 5.6 mm or more is challenging, and thus it is produced in a structure with a stacked ceramic film. The stacked space transformer has low productivity because it is difficult to ensure hole clogging and a precise shape. In this research, an ultrasonic horn is designed to manufacture a bulk-type ceramic space transformer through ultrasonic drilling. Vibration characteristics were analyzed according to the ultrasonic horn, and the natural frequency was measured.

• Design & Manufacturing
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• 제16권3호
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• pp.22-27
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• 2022

The demand for new processing technology that can improve productivity is increasing in industries that require large-scale and various products. In response to this demand, a robot machining system with flexibility is required. Because of the low rigidity of the robot, the robot machining system has a large error during machining and is vulnerable to vibration generated during machining. Vibration generated during machining deteriorates machining quality and reduces the durability of the machine. To solve this problem, a stage for fixing the spindle during machining is required. In order to compensate for the robot's low rigidity, a system combining a piezoelectric actuator for generating a large force and a guide mechanism to actuate with a desired direction is required. Since the rigidity of flexible hinges varies depending on the structure, it is important to optimal design the flexible hinge and high-rigidity system. The purpose of this research is to make analytic model and optimize a flexible hinge and to design a high rigidity stage. In this research, to design a flexible hinge stage, a concept design of system for high rigidity and flexure hinge modeling is carried out. Based on analytic modeling, the optimal design for the purpose of high rigidity is finished and the optimal design results is used to check the error between the modeling and actual simulation results.

• Applied Microscopy
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• 제52권
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• 한국재료학회지
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• 제20권4호
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• pp.223-227
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• 2010

Recently, one-dimensional semiconducting nanomaterials have attracted considerable interest for their potential as building blocks for fabricating various nanodevices. Among these semiconducting nanomaterials,, $SnO_2$ nanostructures including nanowires, nanorods, nanobelts, and nanotubes were successfully synthesized and their electrochemical properties were evaluated. Although $SnO_2$ nanowires and nanobelts exhibit fascinating gas sensing characteristics, there are still significant difficulties in using them for device applications. The crucial problem is the alignment of the nanowires. Each nanowire should be attached on each die using arduous e-beam or photolithography, which is quite an undesirable process in terms of mass production in the current semiconductor industry. In this study, a simple process for making sensitive $SnO_2$ nanowire-based gas sensors by using a standard semiconducting fabrication process was studied. The nanowires were aligned in-situ during nanowire synthesis by thermal CVD process and a nanowire network structure between the electrodes was obtained. The $SnO_2$ nanowire network was floated upon the Si substrate by separating an Au catalyst between the electrodes. As the electric current is transported along the networks of the nanowires, not along the surface layer on the substrate, the gas sensitivities could be maximized in this networked and floated structure. By varying the nanowire density and the distance between the electrodes, several types of nanowire network were fabricated. The $NO_2$ gas sensitivity was 30~200 when the $NO_2$ concentration was 5~20ppm. The response time was ca. 30~110 sec.

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.23-29
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• 2010

메모리칩의 제조 과정에서 발생하는 불량 칩 중 한 두개 비트의 결함이 있는 여러 개의 칩들을 모아서 정상 동작하는 메모리 시스템을 구성하는 방법을 제시한다. 여기에서 제시하는 메모리 시스템은 여러 개의 결함 있는 메모리칩을 겹쳐 쌓은 3차원 다층 구조를 가진다. 이들 칩 간의 신호 선은 through silicon via (TSV)를 통하여 연결한다. 각 칩의 결함이 있는 메모리 셀이 포함된 구역이 칩 마다 서로 다르도록 칩을 분류하여 선택한다. 이 메모리들의 결함이 없는 셀 구역만을 모아 조합하여 전체가 결함이 없는 메모리 시스템이 되도록 한다. 독립적인 주소지정 가능한 n 개의 storage block을 가진 메모리 각각에 k 개의 결함 있는 storage block이 있는 경우 k+1 개의 여유 칩이 조합되어야 한다.

• 대한전자공학회논문지SD
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• 제49권3호
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• pp.1-7
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• 2012

본 논문에서는 모바일 정보기기의 배터리 전력 관리를 제어하는 IBS(Intelligent Battery sensor), BMS(Battery Management System) 등의 PMIC(Power Management IC) 기술에 적합한 9b 2MHz 사이클릭 폴딩 ADC(Analog-to-Digital Converter)를 제안한다. 제안하는 ADC는 응용기술에 적합한 고해상도를 만족시키는 동시에 폴딩 신호처리를 사용함으로써 고속 동작이 가능하다. 또한 폴딩 블록의 하나의 단만을 반복적으로 순환하는 구조로 설계되기 때문에 전체 크기가 줄어들 뿐 아니라 전력소모도 최소화 할 수 있다. 제안하는 시제품 ADC는 0.35um 2P4M CMOS 공정으로 제작되었으며, 측정된 INL 및 DNL은 각각 ${\pm}1.5/{\pm}1.0\;LSB$ 이내로 들어온 것을 확인하였다. 또한 2MS/s 동작 속도에서 SNDR 및 SFDR 이 각각 최대 48dB, 60dB이고, 전력 소모는 3.3V 전원 전압에서 110mW 이며 제작된 ADC의 칩 면적은 $10mm^2$이다.

• 한국통신학회논문지
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• 제30권1A호
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• pp.104-112
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• 2005

본 논문에서는 고속, 저전력 8-비트 ADC를 설계하는 기법들을 제안하였다. 비교적 적은 전력 소모를 가지면서 고속으로 동작 시키기 위해 기존의 파이프라인 구조인 MDAC를 이용한 폐쇄형 구조 대신에 개방형 구조를 채택하였다. 또한 Distributed THA와 캐스캐이드 형태의 구조를 이용하여 높은 샘플링 속도에 최적화 하였다. 제안한 각 단의 크로싱 지점을 판별하는 기법은 증폭기의 개수를 줄일 수 있도록 함으로서 저전력과 좁은 면적의 ADC 구현을 가능하게 하였다. 모의 실험 결과 500-MHz의 샘플링 속도와 1.8V 전원 전압에서 테스트에 필요한 디지털 회로까지 포함, 210mW의 전력을 소비함을 확인 할 수 있었다. 또한 1.2Vpp(Differential) 입력 범위와 200-MHz까지의 입력 주파수에서 8-비트에 가까운 ENOB를 가짐을 볼 수 있었다. 설계된 ADC는 $0.18{\mu}m$ 6-Metal 1-Poly CMOS 공정을 이용, $900{\mu}m{\times}500{\mu}m$의 면적을 차지한다.