• ETRI Journal
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• 제34권1호
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• ETRI Journal
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• 제35권2호
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• 한국전자파학회논문지
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• 제12권1호
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• pp.77-83
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• 2001

본 논문에서는 I/O Cable을 가진 일반 통신시스템의 전자파 방사 Mechanism을 분석하여, Design 에 있어 중요한 Parameter을 도출하였다. System 의 경우 I/O Cable, Ventilation Hole 기구물의 Shielding 대책 등이 중요한 EMC design issue가 된다. 일반적인 전자제품에 비해 통신 System 은 다양한 통신을 위한 Cable을 가지므로, I/O Cable의 중요성이 크다. 따라서 I/O Cable의 Coupling mechanism을 실험 및 Simulation 방법에 의해 분석하고, Low Emission을 위한 EMC Design Rule을 제시하였다. 본 EMC Design Rule을 기반으로 통신 System의 Design을 실현하여, 제품의 Redesign 및 복잡한 Debug과정이 없이 효과적으로 전자파 양립성 규격을 만족한 예를 제시하였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.423-424
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• 2008

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

• 한국산학기술학회논문지
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• 제9권1호
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• pp.41-46
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• 2008

임베디드 소프트웨어는 대상 시스템의 내부 자원과 호스트 시스템의 환경에 매우 민감하므로 수행시 대상 시스템과 동일한 환경에서 디버깅해야 한다. 그러나 대상 시스템의 자원에 직접적으로 접근하여 시스템 상태를 조사하거나 제어하는 기법들은 내부 신호나 자원에 대한 접근이 제한되어 있는 SoC (System-On-a-Chip) 소프트웨어를 디버깅하기는 부적합하다. 본 논문에서는 JTAG을 기반으로 원격 시스템에 접근하여 임베디드 소프트웨어를 디버깅할 수 있는 어뎁터를 제안한다. 이는 원격 디버깅을 위한 환경 구축에 많은 어려움 있는 기존의 환경 구축의 경제적 제한점을 해소할 수 있다. 따라서 본 논문은 원격 시스템내의 임베디드 소프트웨어를 디버깅할 수 있는 경제적인 인터페이싱 환경을 제공한다.

• 대한전자공학회논문지
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• 제25권8호
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• pp.1010-1018
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• 1988

This paper proposes a MOS circuit extractor which extracts a netlist from the hierarchical mask information, for the verification tools. To utilize the regularity and the simple representation of the hierarchical circuit, and to reduce the debug cycle of design, verification, and modification, we propose a hierarvhical and incremental circuit extraction algorithm. In flat circuit extraction stage, the multiple storage quad tree is used as an internal data structure. Incremental circuit extraction using the hierarchical structure is made possible, to reduce the re-extraction time of the modified circuit.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.281-284
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• 2008

본 논문에서는 멀티미디어 SoC 플랫폼의 ASIC 설계에 대해 기술한다. 구현된 플랫폼은 32비트 OpenRISC1200 마이크로프로세서, WISHBONE 온 칩 버스, VGA 제어기, 디버그 인터페이스, SRAM 인터페이스 및 UART로 구성된다. 32 비트 OpenRISC1200 프로세서는 명령어 버스와 데이터 버스가 분리된 하버드 구조와 5단 파이프라인 구조를 가지고 VGA 제어기는 메모리로부터 읽은 이미지 파일에 대한 데이터를 RGB 값으로 CRT 혹은 LCD에 출력한다. 디버그 인터페이스는 플랫폼에 대한 디버깅 기능을 지원하고 SRAM 인터페이스는 18비트 어드레스 버스와 32비트 데이터 버스를 지원한다. UART는 RS232 프로토콜을 지원하는 시리얼 통신 기능을 제공한다. 본 플랫폼은 Xilinx VIRTEX-4 XC4VLX80 FPGA에 설계 및 검증되었다. 테스트 코드는 크로스 컴파일러로 생성되었고 JTAG 유틸리티 소프트웨어와 gdb를 이용하여 패러럴 케이블을 통해 FPGA 보드로 다운로드 하였다. 이 플랫폼은 최종적으로 Chartered 0.18um 공정을 이용하여 단일 ASIC 칩으로 구현 되었으며 100MHz 클록에서 동작함을 확인하였다.

• 전자공학회논문지A
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• 제31A권5호
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• pp.158-169
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• 1994

It is very common in today 's design practice to simulate a big design with a large set of test vectors thereby generating a huge set of data (simulation results) to be analyzed. As the design grows, the simulation results grow and become harder to handled. In this paper, we present algorithms for the compression and regeneration of simulation results. The compression is performed by sampling nets in a circuit. If the user wants to examine the lost part of the data, it is quickly regenerated by applying incremental simulation technique. Experimental results obtained for several practical circuits show that the compression ratio of 10 is easily obtained while maintaining a reasonably fast regeneration of data on a 15.7 MIPS workstation. Using the proposed method we can effectively reduce debug cycle time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
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• pp.67-70
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• 2000

In a distributed real-time system(DRTS), testing and debugging are difficult and critical procedures since they implies several problems like probe effects, nondeterminism, and complex communication patterns. In this paper, we describe the design and implementation of a real-time monitor for ARM processors which are frequently used for embedded applications. The focus of design is to help users debug real-time programs while minimizing the probe effect. Our monitor provides cross debugging features like down-loading from host, break-point based debugging features, and watch-point debugging features for real-time applications. We developed the debugger for ARM processor and debugger has been used for kernel program.