대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 2008년도 하계종합학술대회
- /
- Pages.423-424
- /
- 2008
16 비트 RISC 프로세서 설계 및 검증
Design & Verification of 16 Bit RISC Processor
- 정승표 (부산대학교 전자전기공학과) ;
- 송승원 (부산대학교 전자전기공학과) ;
- 이동훈 (부산대학교 전자전기공학과) ;
- 김강주 (삼성 전기) ;
- 조군식 (삼성 전기) ;
- 박주성 (부산대학교 전자전기공학과)
- Jung, Seung-Pyo (School of Electronic and Electrical Engineering) ;
- Song, Seung-Won (School of Electronic and Electrical Engineering) ;
- Lee, Dong-Hoon (School of Electronic and Electrical Engineering) ;
- Kim, Kang-Joo (Samsung Elector-mechanics) ;
- Cho, Koon-Shik (Samsung Elector-mechanics) ;
- Park, Ju-Sung (School of Electronic and Electrical Engineering)
- 발행 : 2008.06.18
초록
The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.
키워드