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http://dx.doi.org/10.4218/etrij.13.0112.0487

Easily Adaptable On-Chip Debug Architecture for Multicore Processors  

Xu, Jing-Zhe (Department of Electronics and Electrical Engineering, Pusan National University)
Park, Hyeongbae (Department of R&D HW3 Team, Chips & Media Inc.)
Jung, Seungpyo (Department of Electronics and Electrical Engineering, Pusan National University)
Park, Ju Sung (Department of Electronics and Electrical Engineering, Pusan National University)
Publication Information
ETRI Journal / v.35, no.2, 2013 , pp. 301-310 More about this Journal
Abstract
Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.
Keywords
JTAG; on-chip debugger; on-chip debug architecture; multicore processor debugging; monitoring mode debugging;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 W. Wolf, A. Jerraya, and G. Martin, "Multiprocessor System-on- Chip (MPSoC) Technology," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, Oct. 2008, pp. 1701-1713.   DOI   ScienceOn
2 T. Dorta et al., "Overview of FPGA-Based Multiprocessor Systems," Int. Conf. Reconfigurable Comput. FPGAs, 2009, pp. 273-278.
3 G. Martin, "Overview of the MPSoC Design Challenge," 43rd ACM/IEEE Design Autom. Conf., 2006, pp. 274-279.
4 Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core- Based System Chips," Computer, vol. 32, no. 6, June 1999, pp. 52-60.
5 A.B.T. Hopkins and K.D. McDonald-Maier, "Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores," IEEE Trans. Comput., vol. 55, no. 2, Feb. 2006, pp. 174-184.   DOI   ScienceOn
6 ARM Ltd. Embedded-ICE Block Specification. Available: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0180a/DDI0 180.pdf
7 ARM Ltd. ETM (Embedded Trace Marcocell) Block Specification. Available: http://www.arm.com
8 MIPS Technologies Inc. EJTAG Trace Control Block Specification. Available: http://www.mips.com/securedownload/ index.dot?product _name=/auth/MD00148%2D2B%2DETCB%2DSPC%2D01.04.pdf
9 JTAGPPC Controller. Available: http://www.xilinx.com/products/ intellectual-property/jtagppc_cntlr.htm
10 L. Lian et al., "Design and Implementation of A Debugging System for OpenRISC Processor," 2nd ASID Conf., Aug. 2008, pp. 368-371.
11 PDtraceTM Interface Specification, MD00136, May 14, 2003. Available: http://www.mips.com
12 ARM Ltd. Monitor Debug-Mode Block Specification. http://www. arm.com
13 IEEE Std. 1149.1a-1993, "Test Access Port and Boundary-Scan Architecture," Piscataway, NJ: IEEE, 1993.
14 H. Park et al, "On-Chip Debug Architecture for Multicore Processor," ETRI J., vol. 34, no. 1, Feb. 2012, pp. 44-54.   DOI
15 R. Stallman, R. Pesch, and S. Shebs, "GDB User Manual: Debugging With GDB (The GNU Source-Level Debugger)," Free Software Foundation.
16 B. Gatliff, "Embedding with GNU: The GDB Remote Serial Protocol," Red Hat Developer Network (RHDN), 1999.
17 M. Tan, A Minimal GDB Stub for Embedded Remote Debugging, 2002. Available: http://www1.cs.columbia.edu/-sedwards/ classes/2002/w4995-02/tan-final.pdf
18 S. Shebs, GDB: An Open Source Debugger for Embedded Development, Red Hat, 2000.
19 Robert Pizzi, "GNU GDB Internal Architecture," 1993.
20 J. Gilmore and S. Shebs, GDB Internals, Cygnus Solutions, 2004. Available: www.gnuarm.com/pdf/gdbint.pdf
21 J. Bennett "Howto: Porting the GNU Debugger: Practical Experience with the OpenRISC 1000 Architecture," Nov. 2008. Available: http://www.embecosm.com/download/ean3.html
22 N. Stollon et al., "Multi-core Embedded Debug for Structured ASIC Systems," Proc. Design Con, 2004.
23 Open On-Chip Debugger. Available: http://openocd.berlios. de/web/
24 CoreSight On-Chip Trace and Debug Specification. Available: http://www. arm.com
25 L. Fiorin, G. Palermo, and C. Silvano., "MPSoCs Run-Time Monitoring through Networks-on-Chip," Proc. Conf. Design, Automation Test Europe, 2009, pp. 558-561.
26 B. Vermeulen and S. Bakker, ''Debug Architecture for the En-II System Chip,'' IET Comput. Digit. Techn., vol. 1, no. 6, Nov. 2007, pp. 678-684.   DOI   ScienceOn
27 R. Leatherman and N. Stollon, "An Embedded Debugging Architecture for SoCs," IEEE Potentials, vol. 24, no. 1, 2005, pp. 12-16.
28 S. Tang and Q. Xu, "A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-core Transactions in NoC Based Systems," Proc. Asia South Pacific Design Autom. Conf., Seoul, Rep. of Korea, 2008, pp. 416-421.