• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• ETRI Journal
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• v.35 no.2
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• pp.301-310
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• 2013

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.77-83
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• 2001

We analyzed the mechanism of EM emission in telecommunication system and extracted the dominant parameter in EMC design. The I/O cable, ventilation hole and shield design of chassis are important EMC design Issues in telecommunication systems. Because telecommunication systems have much more I/O cables than other electronic products, EMC design of I/O cable is very important in telecommunication systems. Therefore by the method of experimentation and simulation, EM coupling mechanism of I/O cable was analyzed and the design rule for low emission was extracted. On the base of these EMC design rules, EMC design of telecommunication system was executed without complex redesign or debug. The result obtained by these methods was shown in this paper.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.423-424
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• 2008

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.1
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• pp.41-46
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• 2008

Since embedded software is sensitive to the resources and environment of target system, it should be debugged in the same environment as actual target system. However, existing tools to debug embedded software, in which access to internal signal or resources is limited, are uneconomical. In the thesis, economical and practical JTAG Adapter that can use open GDB is suggested. It can remove existing limitations of environment implementation that have many difficulties in implementing an environment for remote debugging. Hence, the thesis provides economical interfacing environment that can debug ubiquitous embedded software inside remote system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.1010-1018
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• 1988

This paper proposes a MOS circuit extractor which extracts a netlist from the hierarchical mask information, for the verification tools. To utilize the regularity and the simple representation of the hierarchical circuit, and to reduce the debug cycle of design, verification, and modification, we propose a hierarvhical and incremental circuit extraction algorithm. In flat circuit extraction stage, the multiple storage quad tree is used as an internal data structure. Incremental circuit extraction using the hierarchical structure is made possible, to reduce the re-extraction time of the modified circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.158-169
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• 1994

It is very common in today 's design practice to simulate a big design with a large set of test vectors thereby generating a huge set of data (simulation results) to be analyzed. As the design grows, the simulation results grow and become harder to handled. In this paper, we present algorithms for the compression and regeneration of simulation results. The compression is performed by sampling nets in a circuit. If the user wants to examine the lost part of the data, it is quickly regenerated by applying incremental simulation technique. Experimental results obtained for several practical circuits show that the compression ratio of 10 is easily obtained while maintaining a reasonably fast regeneration of data on a 15.7 MIPS workstation. Using the proposed method we can effectively reduce debug cycle time.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.67-70
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• 2000

In a distributed real-time system(DRTS), testing and debugging are difficult and critical procedures since they implies several problems like probe effects, nondeterminism, and complex communication patterns. In this paper, we describe the design and implementation of a real-time monitor for ARM processors which are frequently used for embedded applications. The focus of design is to help users debug real-time programs while minimizing the probe effect. Our monitor provides cross debugging features like down-loading from host, break-point based debugging features, and watch-point debugging features for real-time applications. We developed the debugger for ARM processor and debugger has been used for kernel program.