• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.950-953
• /
• 2003

In this paper, sigma-delta A/D converter for ADSL modems using oversampling technique is designed. Conventionally, the oversampling A/D converter is consist of opamps, switched capacitors, quantizers, infernal D/A converters, and decimation filters. 3-bit flash A/D converter, 3-bit thermometer-based D/A converters, and sub-blocks are used for high speed operation. HSPICE simulator and CADENCE tool are used for verification and layout of the designed modulator. The internal A/D converter and D/A converters are operated at 130 MHz. In design of decimation filter Matlab is used for calculating coefficients and ModelSim and VHDL are used for design.

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.1025-1030
• /
• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Journal of IKEEE
• /
• v.18 no.2
• /
• pp.192-197
• /
• 2014

In this paper, $3^{rd}$ SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input range is proposed. Conventional architecture with $3^{rd}$ transfer function is just made as adding a digital delay path in $2^{nd}$ SDM architecture. But the input range is very small because feedback path into the first integrator is increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so input range could be improved about 9dB. The $3^{rd}$ SC SDM with only one operational amplifier was implemented using double-sampling technique. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of $700{\mu}W$ and Dynamic Range of 82.8dB.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.64-72
• /
• 2010

This paper presents a wide range VCO with fine coarse tuning step using a sigma-delta modulation technique for UWB frequency synthesizer. The proposed coarse tuning scheme provides the low effective frequency resolution without any degradation of phase noise performance. With three steps coarse tuning, the VCO has wide tuning range and fine tuning step simultaneously. The frequency synthesizer with VCO was implemented with 0.13 ${\mu}m$ CMOS technology. The tuning range of the VCO is 5.8 GHz~6.8 GHz with the effective frequency resolution of 3.9 kHz. It achieves the measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range 16.8 % with 5.9 mW power. The figure-of-merit with the tuning range is -181.5 dBc/Hz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.4
• /
• pp.630-638
• /
• 2001

This paper has been proposed a structure composed of FIRs and IIR filters as digital decimation filter to compensate the drooping inband on the high precision AU chips. The area of chip has been reduced compared with the conventional structure because the RAM and MAC is reduced. The passband ripple$(\leq\; 0.4535 \times fs)$, passband attenuation(at $\; 0.4535 \times fs$ and stopband attenuation$(\geq\; 0.59\times fs)$ of the 6th-order $\Delta\Sigma$ modulator and digital decimation filter had $\pm0.0007[dB]$, -0.0013[dB] and -110[dB] respectively. Also the inband group delay, which was almost same compared with the conventional digital decimation filter structure, was 30.07/fs[s] band the error of group delay was 0.1672%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.96-100
• /
• 2015

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.75-78
• /
• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• 전자공학회논문지 IE
• /
• v.46 no.1
• /
• pp.1-6
• /
• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.608-614
• /
• 2015

A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

• Journal of Sensor Science and Technology
• /
• v.27 no.1
• /
• pp.21-24
• /
• 2018

A temperature sensor with a binary output was implemented using switched-capacitor circuits in a $0.35-{\mu}m$ CMOS(com-plementary metal-oxide semiconductor) process. The measured temperature exhibited good agreement with the oven temperature after calibration. The measured power consumption was 5.61 mW, slightly lower than the simulated power consumption of 6.63 mW.