JSTS:Journal of Semiconductor Technology and Science

  • 제15권1호
  • /
  • Pages.96-100
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

  • Lim, Hyun-Wook (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kong, Bai-Sun (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Jun, Young-Hyun (Samsung Electronics)
  • 투고 : 2014.06.09
  • 심사 : 2014.11.13
  • 발행 : 2015.02.28
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초록

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

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참고문헌

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