• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.3
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• pp.31-35
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• 2009

In this paper, tunable 4th order SC(switched capacitor) bandpass ${\sigma}-{\Delta}$(Sigma-Delta) modulator with advanced architecture that can adjust the IF by two coefficient values is proposed for data conversion in the wireless communication. Its architecture can optionally adjust all the 4th order noise transfer function in comparison with the conventional architecture. In order to adjust the IF, the conventional architecture needs the four variable coefficients values, basic clocks and eight clocks. On the other hand, the proposed architecture can adjust the IF by two variable coefficient values and basic clocks only.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.135-139
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• 2008

In this paper, tunable SC(switched capacitor) 2nd order bandpass $\Sigma-\Delta$(Sigma-Delta) modulator with novel architecture that can adjust the IF band center frequency by one coefficient value is proposed for data conversion in the IF(Intermediate Frequency) band. Its architecture can optionally adjust all the 2nd order noise transfer function in comparison with the conventional architecture. In order to adjust the center frequency, the conventional architecture needs the two variable coefficient values, basic clock and eight clocks. On the other hand, the proposed architecture can adjust the center frequency by one variable coefficient value and basic clock only.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1558-1563
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• 2007

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1310-1318
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• 1998

Sigma-delta converter is frequently used for conyerting low-frequency anglog to digital signal. The converter consists of a modulator and a digital filer, but our work is concentrated on the modulator. In this works, to design second-order sigma-dalta modulator with 14bit resolution, we define maximumerror limits of each components (operational smplifier, integrator, internal ADC, and DAC) of modulator. It is first performed modeling of an ideal second-order sigma-delta modulator. This is then modified by adding the non-ideal factors such as limit of op-amp output swing, the finit DC gain of op-amp slew rate, the integrator gian error by the capacitor mismatch, the ADC error by the cmparator offset and the mismatch of resistor string, and the non-linear of DAC. From this modeling, as it is determined the specification of each devices requeired in design and the fabrication error limits, we can see the final performance of modulator.

• Communications for Statistical Applications and Methods
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• v.16 no.5
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• pp.841-849
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• 2009

Let {$X_n$, n ${\ge}$ 1} be a negatively associated sequence of identically distributed random variables with mean zeros and positive finite variances. Set $S_n$ = ${\Sigma}^n_{i=1}\;X_i$. Suppose that 0 < ${\sigma}^2=EX^2_1+2{\Sigma}^{\infty}_{i=2}\;Cov(X_1,\;X_i)$ < ${\infty}$. We prove that, if $EX^2_1(log^+{\mid}X_1{\mid})^{\delta}$ < ${\infty}$ for any 0< ${\delta}{\le}1$, then $\lim_{{\epsilon}\downarrow0}{\epsilon}^{2{\delta}}\sum_{{n=2}}^{\infty}\frac{(logn)^{\delta-1}}{n^2}ES^2_nI({\mid}S_n{\mid}\geq{\epsilon}{\sigma}\sqrt{nlogn}=\frac{E{\mid}N{\mid}^{2\delta+2}}{\delta}$, where N is the standard normal random variable. We also prove that if $S_n$ is replaced by $M_n=max_{1{\le}k{\le}n}{\mid}S_k{\mid}$ then the precise rate still holds. Some results in Fu and Zhang (2007) are improved to the complete moment case.

• Korean Journal of Clinical Laboratory Science
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• v.37 no.2
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• pp.65-70
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• 2005

Those specifications of the CLIA analytical tolerance limits are consistent with the performance goals in Six Sigma Quality Management. Six sigma analysis determines performance quality from bias and precision statistics. It also shows if the method meets the criteria for the six sigma performance. Performance standards calculates allowable total error from several different criteria. Six sigma means six standard deviations from the target value or mean value and about 3.4 failures per million opportunities for failure. Sigma Quality Level is an indicator of process centering and process variation total error allowable. Tolerance specification is replaced by a Total Error specification, which is a common form of a quality specification for a laboratory test. The CLIA criteria for acceptable performance in proficiency testing events are given in the form of an allowable total error, TEa. Thus there is a published list of TEa specifications for regulated analytes. In terms of TEa, Six Sigma Quality Management sets a precision goal of TEa/6 and an accuracy goal of 1.5 (TEa/6). This concept is based on the proficiency testing specification of target value +/-3s, TEa from reference intervals, biological variation, and peer group median mean surveys. We have found rules to calculate as a fraction of a reference interval and peer group median mean surveys. We studied to develop total error allowable from peer group survey results and CLIA 88 rules in US on 19 items TP, ALB, T.B, ALP, AST, ALT, CL, LD, K, Na, CRE, BUN, T.C, GLU, GGT, CA, phosphorus, UA, TG tests in chematology were follows. Sigma level versus TEa from peer group median mean CV of each item by group mean were assessed by process performance, fitting within six sigma tolerance limits were TP ($6.1{\delta}$/9.3%), ALB ($6.9{\delta}$/11.3%), T.B ($3.4{\delta}$/25.6%), ALP ($6.8{\delta}$/31.5%), AST ($4.5{\delta}$/16.8%), ALT ($1.6{\delta}$/19.3%), CL ($4.6{\delta}$/8.4%), LD ($11.5{\delta}$/20.07%), K ($2.5{\delta}$/0.39mmol/L), Na ($3.6{\delta}$/6.87mmol/L), CRE ($9.9{\delta}$/21.8%), BUN ($4.3{\delta}$/13.3%), UA ($5.9{\delta}$/11.5%), T.C ($2.2{\delta}$/10.7%), GLU ($4.8{\delta}$/10.2%), GGT ($7.5{\delta}$/27.3%), CA ($5.5{\delta}$/0.87mmol/L), IP ($8.5{\delta}$/13.17%), TG ($9.6{\delta}$/17.7%). Peer group survey median CV in Korean External Assessment greater than CLIA criteria were CL (8.45%/5%), BUN (13.3%/9%), CRE (21.8%/15%), T.B (25.6%/20%), and Na (6.87mmol/L/4mmol/L). Peer group survey median CV less than it were as TP (9.3%/10%), AST (16.8%/20%), ALT (19.3%/20%), K (0.39mmol/L/0.5mmol/L), UA (11.5%/17%), Ca (0.87mg/dL1mg/L), TG (17.7%/25%). TEa in 17 items were same one in 14 items with 82.35%. We found out the truth on increasing sigma level due to increased total error allowable, and were sure that the goal of setting total error allowable would affect the evaluation of sigma metrics in the process, if sustaining the same process.

• Journal of Korean Ophthalmic Optics Society
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• v.6 no.2
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• pp.11-16
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• 2001

The polariscope to measure :he stress in lens was made up quarter-wave plate polarizer and we analyzed two components of light's wave $E_1$ and $E_2$ following the steps. It is clear that the principal-stress difference ${\sigma}_1-{\sigma}_2$ can be determined in 2-D model if fringe order N is measured each point in sample moreover. the optical axes of sample coincide with the principal-stress directions. The birefringence acted to a light wave and a phase retardation were in proportioned to the principal-stressed difference (${\sigma}_1-{\sigma}_2$) and the intensity of final light wave was proportioned to $sin^2({\Delta}/2)$, when ${\Delta}/2=n^{\pi}$ (n=0, 1, 2, ...) and the extinction occurs. As a experimental result, the extinction band shifted owing to a magnitude of lens' external stress.

• East Asian mathematical journal
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• v.38 no.1
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• pp.1-12
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• 2022

Let R be a ring with an endomorphism σ and a σ-derivation δ. R is called (σ, δ)-Baer (resp. (σ, δ)-quasi-Baer, (σ, δ)-p.q.-Baer, (σ, δ)-p.p.) if the right annihilator of every right (σ, δ)-set (resp., (σ, δ)-ideal, principal (σ, δ)-ideal, (σ, δ)-element) of R is generated by an idempotent of R. In this paper, for a given Ore extension A = R[x; σ, δ] of R, the following properties are investigated: If R is a σ-rigid ring in which σ and δ commute, then (1) R is (σ, δ)-Baer if and only if R is (σ, δ)-quasi-Baer if and only if A is (${\bar{\sigma}},\;{\bar{\delta}}$)-Baer if and only if A is (${\bar{\sigma}},\;{\bar{\delta}}$)-quasi-Baer; (2) R is (σ, δ)-p.p. if and only if R is (σ, δ)-p.q.-Baer if and only if A is (${\bar{\sigma}},\;{\bar{\delta}}$)-p.p. if and only if A is (${\bar{\sigma}},\;{\bar{\delta}}$)-p.q.-Baer.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.26-32
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• 2017

This paper presents a low power and high resolution incremental delta-sigma ADC that utilizes a passive integrator instead of an opamp-based active integrator. Opamp is a power-hungry block that involves tight design tradeoffs. To avoid the use of active integrator, the s-domain characteristic of an active integrator is first analyzed. Based on the analysis, an active integrator with low gain design is proposed as an alternative design method. To save power even more aggressively, a passive integrator with no static current is proposed. A 1st order single-bit incremental delta-sigma ADC using the proposed passive integrator is implemented in a 65nm CMOS process. Transistor-level simulation shows that the ADC consumes only 0.6uW under 1.2V supply while achieving SNDR of 71dB with 22kHz bandwidth. The estimated total power consumption including digital filter is 6.25uW, and resulting power efficiency is on a par with state-of-the-art A/D converters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.51-59
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• 2009

This paper presents the design of continuous-time sigma-delta modulator for acoustic sensor. The feedforward structure without summing block is used to reduce power consumption of sigma-delta modulator. A high-linearity active-RC filter is used to improve resolution of sigma-delta modulator. Excess loop delay problem in conventional continuous-time sigma-delta modulators is solved by our proposed architecture. A low power, high resolution fourth-order continuous-time sigma-delta modulator with 1-bit quantization was realized in a 0.13-${\mu}m$ 1-Poly 8-metal CMOS technology, with a core area of $0.58\;mm^2$. Simulation results show that the modulator achieves 91.3-dB SNR over a 25-kHz signal bandwidth with an oversampling ratio of 64, while dissipating $290{\mu}W$ from a 3.3-V supply.