• Title/Summary/Keyword: Deep Trench

Search Result 68, Processing Time 0.025 seconds

The Research of Deep Junction Field Ring using Trench Etch Process for Power Device Edge Termination

  • Kim, Yo-Han;Kang, Ey-Goo;Sung, Man-Young
    • Journal of IKEEE
    • /
    • v.11 no.4
    • /
    • pp.235-238
    • /
    • 2007
  • The planar edge termination techniques of field-ring and deep junction field-ring were investigated and optimized using a two-dimensional device simulator TMA MEDICI. By trenching the field ring site which would be implanted, a better blocking capability can be obtained. The results show that the p-n junction with deep junction field-ring can accomplish near 30% increase of breakdown voltage in comparison with the conventional field-rings. The deep junctionfield-rings are easy to design and fabricate and consume same area but they are relatively sensitive to surface charge. Extensive device simulations as well as qualitative analyses confirm these conclusions.

  • PDF

Low Resistance 3.3kV 4H-SiC Trench Shielded DMOSFET (Trench Shield 구조를 갖는 3.3kV급 저저항 4H-SiC DMOSFET)

  • Cha, Kyu-hyun;Kim, Kwang-su
    • Journal of IKEEE
    • /
    • v.24 no.2
    • /
    • pp.619-625
    • /
    • 2020
  • In this paper, we propose a TS-DMOSFET(Trench Shielded DMOSFET) structure in which P+ shielding region is formed in a deeper region than C-DMOSFET(Conventional DMOSFET) and S-DMOSFET(Shielded DMOSFET). Using TCAD simulation to compare the static characteristics of TS-DMOSFET with C- and S-DMOSFET. As for the structure proposed, the doping is followed by the source trench process. Despite the fact that it is a SiC material, this allows it to form a P+ shielding region in a deep area. Followed by completely suppressing the reach-through effect. As a result, when the breakdown voltage of the three structures is 3.3kV, the Ron of TS-DMOSFET is 9.7mΩ㎠. Thus, it is 68% and 54% smaller than the Ron of C-DMOSFET and S-DMOSFET respectively.

Implementation of Electrochemical Methods for Metrology and Analysis of Nano Electronic Structures of Deep Trench DRAM

  • Zeru, Tadios Tesfu;Schroth, Stephan;Kuecher, Peter
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.2
    • /
    • pp.219-229
    • /
    • 2012
  • In the course of feasibility study the necessity of implementing electrochemical methods as an inline metrology technique to characterize semiconductor nano structures for a Deep Trench Dynamic Random Access Memory (DT-DRAM) (e.g. ultra shallow junctions USJ) was discussed. Hereby, the state of the art semiconductor technology on the advantages and disadvantages of the most recently used analytical techniques for characterization of nano electronic devices are mentioned. Various electrochemical methods, their measure relationship and correlations to physical quantities are explained. The most important issue of this paper is to prove the novel usefulness of the electrochemical micro cell in the semiconductor industry.

Oxide Planarization of Trench Structure using Chemical Mechanical Polishing(CMP) (기계화학적 연마를 이용한 트렌치 구조의 산화막 평탄화)

  • 김철복;김상용;서용진
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.15 no.10
    • /
    • pp.838-843
    • /
    • 2002
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure (STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.13 no.9
    • /
    • pp.729-734
    • /
    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

  • PDF

Petrography and Mineral Chemistry of Some Deep Sea Basaltic Rocks from the Western Caroline Ridge and Yap Trench-Arc System (서부 캐롤라인 해령과 얍 해구-열도계의 해저 현무암질암에 대한 암석 기재 및 광물화학)

  • Park Jun-Beom;Kwon Sung-Tack;Ahn Jung-Ho;Kang Jung-Keuk
    • The Journal of the Petrological Society of Korea
    • /
    • v.1 no.1
    • /
    • pp.71-84
    • /
    • 1992
  • This paper reports the results about the petrography and mineral chemistry of 13 representative dredged basaltic rocks from the western Caroline Ridge (WCR) and Yap Trench-Arc system, and provides the chemical and tectonic informations based on the compositions of clinopyroxene phenocrysts. Compositions of olivine phenocrysts in some analyzed samples are Fo$_{86-80}$. Plagioclase phenocrysts have variable compositions ranging from An$_{90}$ to An$_{55}$. The compositions of clinopyroxene phenocrysts vary according to geological environments; titansalite in atoll and guyot of WCR, diopside-augite in trough and bank of WCR, and endiopside in Yap Trench-Arc system. Application of the discrimination schemes proposed by Leterrier et al. (1982) suggests: (1) the samples from atoll-guyot belong to within plate alkali basalt, implying that western CR could be the continuation of eastern CR formed by hot spot magmatism, (2) the samples from the Yap Trench-Arc system with no present-day magmatism clearly indicate the occurrence of orogenic tholeiites presumably related to early island arc magmatisms in this area, however, (3) the samples from the bank and trough do not provide definitive informations, which might indicate the complexity of their origins.

  • PDF

Process Development of Forming of One Body Fine Pitched S-Type Cantilever Probe in Recessed Trench for MEMS Probe Card (멤스 프로브 카드를 위한 깊은 트렌치 안에서 S 모양의 일체형 미세피치 외팔보 프로브 형성공정 개발)

  • Kim, Bong-Hwan
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.1
    • /
    • pp.1-6
    • /
    • 2011
  • We have developed the process of forming one body S-type cantilever probe in the recessed trench for fine-pitched MEMS probe card. The probe (cantilever beam and pyramid tip) was formed using Deep RIE etching and wet etching. The pyramid tip was formed by the wet etching using KOH and TMAH. The process of forming the curved probe was also developed by the wet etching. Therefore, the fabricated probe is applicable for the probe card for DRAM, Flash memory and RF devices tests and probe tip for IC test socket.

Characteristic of GaN Growth on the Periodically Patterned Substrate for Several Reactor Configurations (반응로 형상에 따른 주기적으로 배열된 패턴위의 GaN 성장 특성)

  • Kang, Sung-Ju;Kim, Jin-Taek;Pak, Bock-Choon;Lee, Cheul-Ro;Baek, Byung-Joon
    • Transactions of the Korean Society of Mechanical Engineers B
    • /
    • v.31 no.3 s.258
    • /
    • pp.225-233
    • /
    • 2007
  • The growth of GaN on the patterned substances has proven favorable to achieve thick, crack-free GaN layers. In this paper, numerical modeling of transport and reaction of species is performed to estimate the growth rate of GaN from tile reaction of TMG(trimethly-gallium) and ammonia. GaN growth rate was estimated through the model analysis including the effect of species velocity, thermal convection and chemical reaction, and thermal condition for the uniform deposition was to be presented. The effect of shape and construction of microscopic pattern was also investigated using a simulator to perform surface analysis, and a review was done on the quantitative thickness and shape in making GaN layer on the pattern. Quantitative analysis was especially performed about the shape of reactor geometry, periodicity of pattern and flow conditions which decisively affect the quality of crystal growth. It was found that the conformal deposition could be obtained with the inclination of trench ${\Theta}>125^{\circ}$. The aspect ratio was sensitive to the void formation inside trench and the void located deep in trench with increased aspect ratio.

Bathymetry Change Investigation of the 2011 Tohoku Earthquake

  • Kim, Kwang Bae;Lee, Chang Kyung
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
    • /
    • v.33 no.3
    • /
    • pp.181-192
    • /
    • 2015
  • Bathymetry change due to the 2011 Tohoku (M9.0) earthquake was investigated through satellite altimetry-derived free-air gravity anomalies (SAFAGA) and shipborne measurements. The earthquake occurred at the plate boundaries near the northeastern coast of Japan, where the oceanic plate subducts beneath the continental plate along deep-sea trench. Data analyzed in this study include SAFAGA from Scripps Institution of Oceanography (SIO), shipborne bathymetry (SB) from the U.S. National Geophysical Data Center (NGDC) and the Japan Agency for Marine-Earth-Science And Technology (JAMSTEC). To estimate the bathymetry change, a reference bathymetry before the earthquake was predicted by gravity-geologic method (GGM) and Smith & Sandwell’s (SAS) method. In comparison with the bathymetry models before the earthquake, GGM bathymetry model generated by a tuning density contrast of 17.04 g/cm3 by downward continuation method was selected because it shows better bathymetry in the short wavelength below about 6 km. From the results, remarkable bathymetry change of about ±50 m was found on the west side of the Japan Trench caused by the earthquake.

Trenched-Sinker LDMOSFET (TS-LDMOS) Structure for 2 GHz Power Amplifiers

  • Kim, Cheon-Soo;Kim, Sung-Do;Park, Mun-Yang;Yu, Hyun-Kyu
    • ETRI Journal
    • /
    • v.25 no.3
    • /
    • pp.195-202
    • /
    • 2003
  • This paper proposes a new LDMOSFET structure with a trenched sinker for high-power RF amplifiers. Using a low-temperature, deep-trench technology, we succeeded in drastically shrinking the sinker area to one-third the size of the conventional diffusion-type structure. The RF performance of the proposed device with a channel width of 5 mm showed a small signal gain of 16.5 dB and a maximum peak power of 32 dBm with a power-added efficiency of 25% at 2 GHz. Furthermore, the trench sinker, which was applied to the guard ring to suppress coupling between inductors, showed an excellent blocking performance below -40 dB at a frequency of up to 20 GHz. These results confirm that the proposed trenched sinker should be an effective technology both as a compact sinker for RF power devices and as a guard ring against coupling.

  • PDF