• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.435-438
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• 2004

This paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance. decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor sire is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using $0.18 {\mu}m$ process-based-HSPICE simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.103-104
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• 2012

In the AC module system, mismatch problem between AC power and constant input power is occurred. To solve this problem, electrolytic capacitor is utilized for diminishing power pulsation in PV side. However, it has disadvantages of low life span and weak in temperature. Decoupling method has been studied to reduce the capacitance and replaces electrolytic capacitor to film capacitor. This paper proposes design method for decoupling circuit which bidirectional DC-DC converter using soft switching. Proposed system is verified by design optimization and simulation results.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.146-153
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• 2008

High speed serial link에 적합한 clock multiphase generator용 integrated phase-locked loop (PLL)을 설계하였다. 설계된 PLL은 programmable current mirror를 사용하여 동작 범위 안에서 동일한 loop bandwidth와 damping factor를 가진다. 또한 설계한 PLL 회로 netlists를 가지고 HSPICE 시뮬레이션을 통해 close-loop transfer function과 VCO의 phase noise transfer function을 구하였다. Board 위 칩의 자체 임피던스는 decoupling capacitor의 크기와 위치에 따라 계산된다. 세부적으로, close-loop transfer function에서 gain의 최대값과 VCO noise transfer function에서 gain의 최대값 사이의 주파수범위에서 decoupling capacitor의 크기와 위치에 따른 보드 위 칩의 자체 임피던스를 구하였다. 이를 바탕으로 보드에서의 decoupling capacitor의 크기와 위치가 PLL의 jitter에 어떠한 영향을 미치는지 분석하였다. 설계된 PLL은 1.8V의 동작 전압에서 400MHz에서 2GH의 wide operation range를 가지며 $0.18-{\mu}m$ EMOS공정으로 설계하였다. Reference clock은 100MHz이며 전체 PLL power consumption은 1.2GHz에서 17.28 mW이다.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.71-80
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• 2004

본 논문에서는 집적회로 패키지에 기인한 노이즈를 해석할 수 있는 새로운 SSN모델을 보인다. 기존의 디커플링 커패시터를 고려하지 않은 회로모델은 과도하게 SSN을 예측한다는 것을 보였으며, 디커플링 커패시터가 포함된 패키지 회로모델을 통하여 새로운 SSN 모델을 제안하였다. 새롭게 제안된 SSN 모델은 0.18um공정(TSMC 0.18um공정)을 사용하여 다양한$\cdot$회로설계 변수(입력상승시간, 패키지 인덕턴스 및 동시 스위칭 개수)의 변화에 따라 HSPICE 시뮬레이션과 정확히($5\%$ 이내에서) 일치한다는 것을 검증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.55-56
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• 2012

In general, a power decoupling method using electrolytic capacitor is used to solve a problem that appears 120[Hz] ripple of grid at the PV module output. But electrolytic capacitor has a effect on the short lifetime and low reliability of PV system. Therefore, studies which replace the large electrolytic capacitor with small film capacitor have been researched in resent years. This paper proposes flyback inverter which can be replaced with film capacitor by connecting the circuit implementing zero voltage switching in PV side. The proposed system is validated by PSIM simulation.

• 전력전자학회논문지
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• 제24권3호
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 추계 기술심포지움 논문집
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• pp.23-27
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• 2000

Simultaneous Switching Noise (SSN) propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs) causes malfunction of both digital and analog circuits. To reduce SSN, decoupling capacitors are generally used in the PCBs. In this paper, we improve the equivalent circuit model of decoupling capacitor in high-frequency range to analyze the effect of SSN reduction accurately. The analysis is performed by the microwave and RF design system (MDS) method and the finite difference time domain (FDTD) method. We compared the results by the ideal capacitor model with those by the proposed model.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권4호
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• pp.246-255
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• 2000

This paper deals with a novel full digital control method of the three-phase PWM inverter for UPS. The voltage and current of output filter capacitor as state variables are the feedback control input. In addition, a double deadbeat control consisting of a d-q current minor loop and a d-q voltage major loop, both with precise decoupling, have been developed. The switching pulse width modulation based on SVM is adopted so that the capacitor current should be exactly equal to its reference current. In order to compensate the calculation time delay, the predictive control is achieved by the current·voltage observer. The load prediction is used to compensate the load disturbance by disturbance observer with deadbeat response. The experimental results show that the proposed system offers an output voltage with THD less than 2% at a full nonlinear load.

• 전기학회논문지P
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• 제66권4호
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• pp.236-241
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• 2017

This paper presents a single-phase grid connected voltage-ed inverter with a power decoupling circuit. In the single-phase grid connected voltage-ed inverter, it is well known that a power pulsation with twice the grid frequency is contained in the input power. In a conventional voltage type inverter, electrolytic capacitors with large capacitance have been used in order to smooth the DC voltage. However, lifetime of those capacitors is shortened by the power pulsation with twice grid frequency. The authors have been studied a active power decoupling(APD) method that reduce the pulsating power on the input DC bus line, this enables to transfer the ripple energy appeared on the input DC capacitors into the energy in a small film capacitor on the additional circuit. Hence, extension of the lifetime of the inverter can be expected because the small film capacitor substitutes for the large electrolytic capacitors. Finally, simulation and experimental results are discussed.

• 동굴
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• 제80호
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• pp.21-24
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• 2007

The need for high-frequency decoupling capacitors to supply the transient current requirements to high-speed devices is ubiquitous in current microelectronics applications. Even though materials and their processes have already been developed in terms of their performances, low manufacturing cost cannot be overemphasized in current microelectronics industry. For this reason, we revisited low cost ceramic filled polymer integrated capacitor. Experiments were performed according to the design of experiment (DOE). The best recipe that has the optimized ratio of material composite was obtained using by response optimizer in Minitab. And also, high-frequency measurements were performed to get frequency dependent data using network analyzer.