• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.682-685
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• 2002

In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

• Current Optics and Photonics
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• v.2 no.5
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• pp.453-459
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• 2018

We have developed a high-performance signal-processing and image-rendering heterogeneous computation system for optical coherence tomography (OCT) on mobile processor. In this paper, we reveal it by demonstrating real-time OCT image processing using a Snapdragon 800 mobile processor, with the introduction of a heterogeneous image visualization architecture (HIVA) to accelerate the signal-processing and image-visualization procedures. HIVA has been designed to maximize the computational performances of a mobile processor by using a native language compiler, which targets mobile processor, to directly access mobile-processor computing resources and the open computing language (OpenCL) for heterogeneous computation. The developed mobile image processing platform requires only 25 ms to produce an OCT image from $512{\times}1024$ OCT data. This is 617 times faster than the naïve approach without HIVA, which requires more than 15 s. The developed platform can produce 40 OCT images per second, to facilitate real-time mobile OCT image visualization. We believe this study would facilitate the development of portable diagnostic image visualization with medical imaging modality, which requires computationally expensive procedures, using a mobile processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1185-1194
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• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• 전기의세계
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• v.30 no.12
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• pp.793-796
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• 1981

최근 우리나라에도 digital image processing에 대한 연구가 활발이 진행되고 있다. 또한 digital image processing의 생체공학에의 응용도 괄목할 만하다. 이러한 연구와 응용에 도움이 되고자 microcomputer를 이용한 image processor설계의 실례를 기술하고자 한다. 이 설계는 목적 image를 stationary image로 가정하여 TV카메라의 영상신호를 sample하여 computer 기억장치에 저장하므로 가격이 저렴하게 된다. 이러한 장치로서는 DMA연결 (Direct Memory Access interface)을 사용하여 빠른 data transfer를 달성할 수 있다. Digital image processing계는 기본적으로 microcomputer가 TV카메라와 TV모니터에 연결된 구조를 하고 있다. Computer가 기억장치에 저장된 data를 처리하여 필요한 정보를 얻게 된다. 이러한 data 처리를 하므로서 image를 사용자가 해석하기 쉽도록 image질을 향상시키거나 computer가 image를 인식하게 한다. 이와같이 처리된 image는 TV모니터를 통해서 볼 수 있다. 본지에서는 256x256개의 pixel들로 이루어지고, 각개의 pixel은 4개의 bit로 구성된 image processor의 설계를 기술한다.

• Transactions of Materials Processing
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• v.12 no.6
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• pp.542-549
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• 2003

Three-dimensional forging analysis becomes an inevitable tool to make design process more reliable and more producible. In this study, in order to make the investigation for three-dimensional forging analysis more conveniently and accurately, a new post processor was developed. For post-processing of multi-stage forging simulation, efficient data structure was proposed and applied by using STL. New file architecture was developed to handle successive and huge data efficiently, common in three-dimensional forging analysis. Since sectioning and flow tracing plays an important role in the investigation of analysis result, we developed an algorithm suitable for 4-node and 10-node tetrahedron. This flow tracing algorithm can trace and reverse-trace flow through remeshing. Developed program shows good performance and functionality. Especially, a big size problem can be handled easily due to proposed data structure and file architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.659-662
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• 2005

XML is standard of web document, and is used in language for document data exchange. XML document is used as example that change existing document to XML or makes new document by XML increases and XML search system to search XML document efficiently accordingly is requiring. This paper describes design and implementation of query processing system for translating XML elements and data between XML documents and relational database and consist of XML to DB processor, DB to XML processor and XML document management processor. Through this, described for design and embodiment of efficient XML document search system of JAVA base using XQL that is proposed in language of quality of XML document.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.515-518
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• 1998

This paper describes a direct transfer method of multimedia data stream between multimedia processor and network device without using system memory. The hardware architecture and functions for direct transfer, the method to transfer multimedia data to and from the multimedia processor and etc are described. Comparing the proposed method with general methods, I show that the direct transfer method can decrease number of bus accesses and bus cycles.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.30-38
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• 1995

In this paper, we propose an efficient architecture for motion estimation processor which performs one of essential functions in moving picture coding algorithms. Simple control mechanism of data flow in register array which stores pixel data, parallel processing of pixel data and pipelining scheme in arithmetic umit allow this architecture to process a 352*288 pixel image at the frame rate of 30fs, which is compatable with CCITT standard H.261.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.