The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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A study on the implementation of scalable image capture processor using DRAM

DRAM을 사용한 가변 사이즈 영상 저장/재생 시스템 구현에 관한 연구

  • 이호준 (고려대학교 전자공학과 VLSI and CAD연구실) ;
  • 이주석 (용인공업전문대학 전자과) ;
  • 박노경 (호서대학교 정보통신공학과) ;
  • 차균현 (고려대학교 전자공학과 VLSI and CAD연구실)
  • Published : 1997.06.01
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Abstract

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

Keywords

References

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