• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.76-82
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• 2003

The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel $Al_2O_3/HfO_2$ dielectric material with equivalent oxide thickness (EOT) of 25 ${\AA}$ is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by $Al_2O_3/HfO_2$ dielectric material, respectively.

• 한국세라믹학회지
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• 제34권10호
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• pp.1060-1066
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• 1997

In this paper, the effects of La addition of PLZT thin film prepared by sol-gel method on the capacitor characteristics are investigated for gigabit generation DRAM applications. The addition of La on the PLZT capacitor results in a trade-off between charge storage density(Qc') and leakage current density(Jl). As La content increases, Qc' and permeability(εr) at 0V are reduced while Jl is significantly decreased. It is demonstrated that 5% La doping of PZT can substantially reduce Jl and also improve resistance to fatigue while incurring only minimal degradation of Qc'. Very low leakage current density (5×10-7 A/㎠ even at 125℃) and high charge storage density (100fC/㎛2) under VDD/2=1V conditions are achieved using 5% La doped PZT thin films for gigabit DRAM capacitor dielectrics. In addition, the fatigue and TDDB measurements indicate good reliability of the PLZT capacitors.

• 한국전기전자재료학회논문지
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• 제19권2호
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.45-53
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• 2003

DRAM에서 사용되는 내부 승압 전원 전압과 기판인가 전원 전압 발생기를 공유함으로써 단일 Charge Pump에서 승압 전원과 기판 전원을 동시에 발생시키는 회로를 설계하였다. 이 회로는 0.14um의 DRAM 공정을 사용하여 기존 보다 전력 소모를 30%, 전체 면적을 40% 그리고 Pumping capacitor 면적을 29.6% 각각 감소하였으며 또한 전류 공급 효율을 13.2% 향상 시켰다. Charge Recycling 기법을 적용하여 Pumping capacitor의 Precharge 구간 동안 소모되는 전류를 75% 감소하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.634-639
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• 2001

In this paper, we discuss optimum process conditions of Hemispherical Grained Silicon formation for high density DRAM'S capacitor. In optimum process renditions, the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 40(equation omitted), respectively. in the 64M bit DRAM capacitor using optimum process conditions, limit thickness of nitride is about 65(equation omitted). The results obtained in this study are applicable to process control and HSG-Si formation for high reliability and high density DRAM's capacitor.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1997년도 제12회 학술발표회 논문개요집
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• pp.31-31
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• 1997

• 한국전기전자재료학회논문지
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• 제27권2호
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.436-438
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• 1987

The thermal oxidation recipe has been optimized for very thin (12 nm) capacitor oxide for Mega bit DRAM. The time dependent dielectric breakdown characteristics show that the breakdown voltage and time to breakdown are very high and uniform, indication that our oxide is defect free and suitable for DRAM capacitor dielectric. To our knowledge this is the best oxide quality obtained up tp now around 10 nm.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.157-164
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• 1994

DRAM(Dynamic Random Access Memory)은 반도체 소자중 가장 대표적인 기억소자로, switch역활을 하는 1개의 transistor와 data의 전하를 축적하는 1개의 capacitor로 구성된 단순한 구조와 고집적화에 용이하다는 이점을 바탕으로, supercomputer에서 가전제품 및 산업기기에 이르기 까지 널리 이용되어왔다. 한편으로 DRAM사업은 고가의 장치사업으로 조기시장 진입을 위하여 초기에 막대한 자본투자, 급속한 기술발전, 짧은 life cycle, 가격급락등이 심하여, 시한내 투자회수가 이루어져야 하는 위험도가 큰 기회사업이라는 양면성도 가지고 있다. 이러한 관점때문에 새로운 DRAM기술은 매 세대마다 끊임없이 빠른 속도로 개발되어왔다. 그러나 sub-micron이하의 DRAM세대로 갈수록 그에 대한 신기술은 점차 어렵게 되어가고, 한편으로는 system의 다양화에 따른 요구도 강하여, 이제는 통상적인 DRAM의 고집적화/저가의 전략만으로는 생존하기 어려운 실정이므로 개발전략도 수정하여야만 할 것이다. 이러한 어려운 기술한계를 극복하기 위하여 새로운 소자기술 및 공정개발에 대한 breakthrough가 이루어져야 할 것이다. 이러한 관점에서 현재까지의 DRAM개발 추이와 향후의 기술방향에 관하여 몇가지 중요한 item을 설정하여 논의해 보기로 한다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 춘계 학술발표 강연 및 논문 개요집
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• pp.108-108
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• 1994