• Title/Summary/Keyword: DPDT

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A Study for DPDT Switch Design with Defected Ground Structure (DGS 구조를 이용한 DPDT 스위치 설계에 관한 연구)

  • An Ka-Ram;Jeoung Myeung-Sub;Lim Jae-Bong;Cho Hong-Goo;Park Jun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.3
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    • pp.132-138
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    • 2005
  • In this paper a DPDT(Double-Pole Double Through) switch with defected ground structure(DGS) is proposed. The equivalent circuit for the proposed switch structure is derived according to based on equivalent circuit of proposed DGS unit structure. The equivalent circuit parameters of DGS unit are extracted by using the circuit analysis method. The on/off operation of the proposed switch is obtained by varying the capacitance of the varactor diode at the defected ground plane. In the case of ON state, the insertion loss of the fabricated DPDT was shown under 1dB. And in OFF state, we found the rejection characteristic over 20dB at the designed frequency 2.45GHz. The experimental results show excellent insertion loss at on state and isolation at off state.

Analysis of Via Loss Characteristic in Embedded DPDT Switch Using SoP-L Fabrication (SoP-L 공정을 이용한 DPDT 스위치를 임베딩 할 경우 스위치 특성에 영향을 주는 Via의 loss 분석)

  • Mun, Jong-Won;Gwon, Eun-Jin;Ryu, Jong-In;Park, Se-Hoon;Kim, Jun-Chul
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.557-558
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    • 2008
  • This paper presents the effects of via losses to be connected with an embedded DPDT(Double Pole Double Thru) in a substrate. The substrate consists of two ABF(Ajinomoto Bonding Film) and a Epoxy core. In order to verify and test effects of via, via chains in a substrate using SoP-L process are proposed and measured. Via loss can be calculated as averaging the total via holes. The exact loss of a DPDT switch embedded in substrate are extracted by using the results of via chain and measured data from embedded DPDT. The calculated one via insertion loss is about 0.0005 dB on basis of measured via chains. This result confirms very low loss in via. So the inserti on loss of the embedded switch is confirmed only switch loss as loss is 0.4 dB.

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Developing Tool of Distributed Application Program Based on Distributed Object Group Framework (분산객체그룹 프레임워크 기반 분산응용 프로그램 개발 도구)

  • Lim Jeong-Taek;Shin Chang-Sun;Joo Su-Chong
    • Journal of Internet Computing and Services
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    • v.6 no.6
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    • pp.71-83
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    • 2005
  • In this paper, we developed the Distributed Programming Developing Tool(DPDT) which can make distributed application program efficiency based on the distributed object group framework supporting group management and dynamic binding for object resources requested from clients on distributed systems. The distributed object group framework we constructed provides not only the group register/withdraw, the access right and the name/property services for server objects from a point of view of group management services, but also dynamic binding, replicated object supporting, load balance, and federation among the object groups from a point of view of the supporting services of distributed application, When developing distributed application, by using our tool, server programming developer implements objects in each server system, next registers the properties to need for service provision to the object group. Client programming developer can also develop client program easily by obtaining the access right for the object or the object group and using the properties of objects with the access right permitted to the client. For providing above application developing environment in this paper. we described the definition of object group, the architecture of the distributed object group framework which our tool supports, and its functionalities, then specified the 3 GUI environments of DPDT implemented for providing efficient interfaces between the distributed object group and distributed applications. Finally, by using the DPDT, we showed the group register/withdraw and the access right grant procedure of objects which are server programs, the developing process of client program, and the executing results of the distributed application developed.

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RF-MEMS-Based DPDT Switch on Silicon Substrate for Ku-Band Space-Borne Applications

  • Singh, Harsimran;Malhotra, Jyoteesh
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.1
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    • pp.16-20
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    • 2017
  • A RF-MEMS (radio-frequency microelectromechanical-system) based DPDT (double pole double throw) switch for the Ku band has been designed and analyzed for this article. The switch topology is based on the FG-CPW (finite ground-coplanar waveguide) configuration of a microstrip-transmission line. An FEM-based multiphysics solver is used for the evaluation of the spring constant, stress distribution, and pull-in voltage regarding the requirements of the switch-beam unit. The electromagnetic performance of the switch is investigated for a $675{\mu}m$ thick silicon substrate. For the operational frequency of 14.5 GHz, an insertion loss better than -0.3 dB, a return loss better than -40 dB, and input/output- and output-port isolations better than -35 dB are achieved for the switching unit.

X-Band 6-Bit Phase Shifter with Low RMS Phase and Amplitude Errors in 0.13-㎛ CMOS Technology

  • Han, Jang-Hoon;Kim, Jeong-Geun;Baek, Donghyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.511-519
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    • 2016
  • This paper proposes a CMOS 6-bit phase shifter with low RMS phase and amplitude errors for an X-band phased array antenna. The phase shifter combines a switched-path topology for coarse phase states and a switch-filter topology for fine phase states. The coarse phase shifter is composed of phase shifting elements, single-pole double-throw (SPDT), and double-pole double-throw (DPDT) switches. The fine phase shifter uses a switched LC filter. The phase coverage is $354.35^{\circ}$ with an LSB of $5.625^{\circ}$. The RMS phase error is < $6^{\circ}$ and the RMS amplitude error is < 0.45 dB at 8-12 GHz. The measured insertion loss is < 15 dB, and the return losses for input and output are > 13 dB at 8-12 GHz. The input P1dB of the phase shifter achieves > 11 dBm at 8-12 GHz. The current consumption is zero with a 1.2-V supply voltage. The chip size is $1.46{\times}0.83mm^2$, including pads.

The Fabrication and Characterization of Embedded Switch Chip in Board for WiFi Application (WiFi용 스위치 칩 내장형 기판 기술에 관한 연구)

  • Park, Se-Hoon;Ryu, Jong-In;Kim, Jun-Chul;Youn, Je-Hyun;Kang, Nam-Kee;Park, Jong-Chul
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.3
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    • pp.53-58
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    • 2008
  • In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

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Design of a 6~18 GHz 8-Bit True Time Delay Using 0.18-㎛ CMOS (0.18-㎛ CMOS 공정을 이용한 6~18 GHz 8-비트 실시간 지연 회로 설계)

  • Lee, Sanghoon;Na, Yunsik;Lee, Sungho;Lee, Sung Chul;Seo, Munkyo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.11
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    • pp.924-927
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    • 2017
  • This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

Analysis of Frequency Response Depending on Wire-bonding Length Variation (Wire-bonding의 길이 변화에 따른 주파수별 특성 분석)

  • Gwon, Eun-Jin;Mun, Jong-Won;Ryu, Jong-In;Park, Se-Hoon;Kim, Jun-Chul
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.551-552
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    • 2008
  • This paper presets a results of frequency response in variation of wire bonding length. A gold ball bonding is used as a wire bonding process, and a DPDT(double pole double thru) switch is adapted as a device for test. Wire length is ranged from 442um to 833um and a measured frequency range is from 1 GHz to 6 GHz. Little difference are measured in insertion loss and return loss depending on wire length. Measured S21 and S11 are -0.58 dB and -17.7 dB, respectively. S21 insertion loss is rising up and S11 insertion loss is falling down as the frequency is increased.

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A 5-20 GHz 5-Bit True Time Delay Circuit in 0.18 ㎛ CMOS Technology

  • Choi, Jae Young;Cho, Moon-Kyu;Baek, Donghyun;Kim, Jeong-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.3
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    • pp.193-197
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    • 2013
  • This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

An Experimental Study on Pumping Speed of Disk-Type Drag Pumps for Spiral Channels in Rarefied Gas Flows (희박기체영역에서의 나선형 홈을 가진 원판형 드래그펌프의 배기속도에 관한 실험적 연구)

  • Kwon, Myoung-Keun;Yang, Seoung-Min;Lee, Seung-Jae;Hwang, Young-Kyu;Heo, Joong-Sik
    • Proceedings of the KSME Conference
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    • 2003.04a
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    • pp.2101-2104
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    • 2003
  • Experimental investigations are performed for the rarefied gas flows in a disk-type drag pump (DTDP). The pump considered in this paper consists of grooved spiral channel on rotors and planar stators. The flow-metre method is adopted to calculate the pumping speed. Compression ratio and pumping speeds for the nitrogen gas are measured under the inlet pressure range of $0.001{\sim}4$ Torr. The maximum of compression ratio was about 3300 for three-stage DTDP, 1000 for two-stage and 100 for single-stage DTDP at zero throughput. The number of stage influences the pumping speed of DPDT

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