• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1065-1070
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• 2009

This paper presents the new technique of modeling using Dynamic Link Library(DLL) in ElectroMagnetic Transients Program - Restructured Version(EMTP-RV) in which we have simplified the procedures of OverCurrent Relay(OCR) modeling. The DLL function is designed to allow EMTP-RV users to develop advanced program model modules and interface them directly and intimately with the EMTP-RV engine. The modeled OCR is verified by simulating the various fault cases in the distribution system. Also, the performance for the modeling of OCR using DLL is compared with that of the method using the control components of EMTP-RV and using EMTP/MODELS. The results show the validity of modeled OCR and the effectiveness of the method using DLL function.

• ETRI Journal
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• v.29 no.6
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• pp.716-724
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• 2007

As ultra-wideband impulse radio (UWB-IR) uses short-duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay-locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB-IR time-hopping spread-spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four-branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two-branch DLLs if proper parameters are chosen.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.426-429
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• 2002

The data link layer (DLL) of Foundation Fieldbus (FF) includes both token-passing and scheduling services. Periodic data are transmitted via the scheduling service, while time-critical and time-available data are transmitted via the token-passing service. This study developed a network interface board that implements the DLL of FF. Using the network interface board, this study experimentally evaluates the delay performance of the DLL of FF. This study measured the delay performance with respect to the change of the DLL parameters of FF, and investigated the relationship between the DLL parameters and network performance. The study also compared the experimental results with the results obtained from an analytical model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.1-9
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• 1996

in this paper, we analyzed CDD-DLL code tracking loop for tracking of direct-sequence spread-spectrum signals in a multipath fading channel. The multipath fading channel is modeled as two-ray rayleigh fading channel which is well applicable in a land mobile communication environments. We use trackin jitter variance and mean-time-to-lose-lick as performance measures. From the numerical resutls, it is shown that the effect of multipath fading decreases as SNR/bit increases. Also it is shown that CDD-DLL provides superior jitter performance compared with noncoherent DLL and jitter performance improvement is more significant for a two-ray rayleigh fading channel than an AWGN channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Journal of The Korean Society of Integrative Medicine
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• v.7 no.3
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• pp.61-69
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• 2019

Purpose : The purpose of this study was to investigate the effects of Straight leg lifts (SLL) and double leg lowering (DLL) exercise on abdominal muscle activity, visual analog scale (VAS), and flexibility in patients with chronic low back pain (LBP). Methods : A total of 30 LBP patients were divided into two groups: those with SLL exercise group 15 (male=8, female=7) and those with DLL exercise group 15 (male=7, female=8). Before the intervention, the abdominal muscle activity, VAS, and flexibility were measured. After 4 weeks of intervention, the above variables were measured in the same way. The SLL exercise bends the leg $45^{\circ}$ in the supine position, and the DLL exercise was performed as opposed to SLL. At this time, the pressure biofeedback unit (PBU) was placed behind the lumbar to reduce the instability of the pelvis and muscles. The subjects were instructed to use the PBU to maintain the target pressure determined (40 mmHg) during the exercise. Results : The external oblique (EO), internal oblique (IO), and transverse abdominis (TrA) were significantly different in the SLL and DLL group, and EO, IO, and TrA activity improved more significantly increased in the DLL than SLL group (p<.05). The results on the VAS and flexibility were significantly different both group (p<.05). However, there was no significant difference between the groups (p>.05). Conclusion : SLL and DLL exercises in patients with LBP were able to confirm the increased activity of the abdominal muscles, decreased pain, and increased flexibility of the waist. In addition, DLL exercise is more effective in patients with LBP in terms of muscle activity.

• Journal of IKEEE
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• v.26 no.3
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• pp.380-388
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• 2022

The traditional malware detection technologies collect known malicious programs and analyze their characteristics. Then such a detection technology makes a blacklist based on the analyzed malicious characteristics and checks programs in the user's system based on the blacklist to determine whether each program is malware. However, such an approach can detect known malicious programs, but responding to unknown or variant malware is challenging. In addition, since such detection technologies generally monitor all programs in the system in real-time, there is a disadvantage that they can degrade the system performance. In order to solve such problems, various methods have been proposed to analyze major behaviors of malicious programs and to respond to them. The main characteristic of ransomware is to access and encrypt the user's file. So, a new approach is to produce the whitelist of programs installed in the user's system and allow the only programs listed on the whitelist to access the user's files. However, although it applies such an approach, attackers can still perform malicious behavior by performing a DLL(Dynamic-Link Library) injection attack on a regular program registered on the whitelist. This paper proposes a method to respond effectively to attacks using DLL injection.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of IKEEE
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• v.15 no.1
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.