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http://dx.doi.org/10.9723/jksiis.2013.18.5.009

A Low-power, Low-noise DLL-based Frequency Multiplier for Reference Clock Generator  

Kim, Hyung Pil (강원대학교 전기전자공학전공)
Hwang, In Chul (강원대학교 전기전자공학전공)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.18, no.5, 2013 , pp. 9-14 More about this Journal
Abstract
This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.
Keywords
DLL; VCDL; Phase noise; frequency multiplier;
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