• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1243-1250
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• 2014

In this paper, a wideband DDS module covering the frequency range from 0.5 to 1.1 GHz was designed and fabricated. The clock frequency of the DDS was selected 2.4 GHz in order for 600 MHz output bandwidth. Multiple spurious cancelling signals having same amplitude and $180^{\circ}$ phase difference compared to the spurious were created at the additional path and added to the output signal within DDS for the spurious performance improvement. The fabricated DDS module showed better spurious performance than the commercial DDS one more than 10 dB and frequency tuning time was 340 ns below.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.827-832
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• 2011

Communication is very important in warfare. Dispatch riders were used in ancient warfare, but communication system is used in modern warfare, as the advancement of communication equipments. In order to weaken enemy military strength, communication jamming signal disrupts enemy communication systems. Tone jamming is one of the common communication jamming techniques. Tone jamming is that several tones are placed in the spectrum for neutralizing the enemy's radio communication receivers. In this paper, we develop multitone jamming signal controlled tone number up to 10 tones and tone interval between tones using DDS(Direct Digital Synthesizer) core and FPGA(Field Programmable Gate Arry) of Xilinx Inc. and show the jamming signal output.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1053-1056
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• 2005

This paper proposes a design technique of DDS (Direct Digital Synthesizer) to reduce the ROM size, and also describes the procedure of the implementation of the technique. Unlike other techniques suggested so far, the proposed technique is able to reduce the ROM size to a great extent with minimal hardware overheads. The frequencies of the signal synthesized by the implemented DDS accurately changed with the applied frequency control words.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.333-339
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• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.607-610
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• 2006

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with hish speed frequency hopping rate and high frequency resolution characteristics was implemented in this paper. The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which ate also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provide the spurious suppression characteristic of -50 dBc, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represent the amplitude flatness of 3 dB and less in the pass-band and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.223-228
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• 2007

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with high speed frequency hopping rate and high frequency resolution characteristics was designed and implemented in this paper The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which are also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provides the spurious suppression characteristic of -50 dBc and less, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represents the amplitude flatness of 3 dB and less in the pass-band, and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.