• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.45-46
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• 2012

본 논문에서는 멀티레벨 인버터에서 발생하는 DC Link 단의 커패시터 불 평형 문제를 해결하고자 새로운 DC 전압 균형을 위한 스위칭 방식에 대해 제안한다. 제안한 방식은 DC-Link 단에 위치한 각각의 커패시터들의 전압을 센싱하고 이를 PI제어를 통해 스위칭 신호를 제어함으로써 각각의 커패시터에 걸리는 전압을 균일하게 만듦으로써, 커패시터단의 전압 불 평형을 개선하였으며, 이를 3상 2레벨 멀티-레벨 인버터를 이용한 시뮬레이션 결과를 통해 본 논문의 타당성을 검증하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.1
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• pp.61-69
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• 2005

The topology of NPC inverter coupled with the large number of devices used increases the probability of device failure. It's necessary to develop an optimal remedial strategy which can be used to continue the application when fault occurs. The fault tolerance is obtained by the use of the proposed method. The proposed method utilizes that the one phase load with the failed power device could be connected to the center-tap of the DC-link capacitor in order to dc-link voltage with balance and the sinusoidal phase current with constant amplitude under the single power device fault condition. The strategy described in this paper is expected to provide an economic alternative to more expensive redundancy techniques.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
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• v.14 no.3
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• pp.519-530
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• 2014

A novel simplified pulse width modulation(PWM) strategy for neutral point clamped (NPC) three-level converter is proposed in this paper.The direct output voltage modulation is applied to reduce the calculation time. Based on this strategy, several optimized control methods are proposed. The neutral point potential balancing algorithm is discussed and a fine neutral point potential balancing scheme is introduced. Moreover, the minimum pulse width compensation and switching losses reduction can be easily achieved using this modulation strategy. This strategy also gains good results even with the unequal DC link capacitor. The modulation principle is studied in detail and the validity of this simplified PWM strategy is experimentally verified in this paper. The experiment results indicated that the proposed PWM strategy has excellent performance, and the neutral point potential can be balanced well with unequal DC link captaincies.

• Journal of Power Electronics
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• v.14 no.2
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• Journal of Power Electronics
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• v.14 no.3
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• pp.499-506
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• 2014

This paper proposes a 3 kW single-phase bi-directional multi-level converter for energy storage applications. The proposed topology is based on the H-bridge structure with four switches connected to the DC-link. A simple phase opposition disposition PWM method that requires only one carrier signal is also suggested. The switching sequence to balance the capacitor voltage is considered. The topology can be extended to a nine-level converter or a three-phase system. The operating principle of the proposed converter is verified through a simulation and an experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.2
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• pp.115-122
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• 2007

In this paper, a novel fault detection method for fault tolerant control is proposed when the NPC inverter has a open failure in the switching device. The open fault of switching device is detected by checking the variation of a leg-voltage in the neutral-point-clamped inverter and the two phases control method is used for continuously balance the three phases voltage to the load. It can be achieve the fault tolerant control for improving the reliability of the NPC inverter by the fault detection and reconfiguration. This method has fast detection ability and a simple realization for fault detection, compared with a conventional method. Also, this fast detection ability improved the harmful effects such as DC-link voltage unbalance and overstress to other switching devices from a delay of fault detection. The proposed method has been verified by simulation and experiment.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1176-1189
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• 2016

In this paper, a novel quasi-direct power control (Q-DPC) scheme based on a resonant frequency adaptive proportional-resonant (PR) current controller with a variable frequency resonant phase locked loop (RPLL) is proposed, which can achieve a fast power response with a unity power factor. It can also adapt to variations of the generator frequency in T-type Three-level shaft synchronous generator (SSG) converters. The PR controller under the static α-β frame is designed to track ac signals and to avert the strong cross coupling under the rotating d-q frame. The fundamental frequency can be precisely acquired by a RPLL from the generator terminal voltage which is distorted by harmonics. Thus, the resonant frequency of the PR controller can be confirmed exactly with optimized performance. Based on an instantaneous power balance, the load power feed-forward is added to the power command to improve the anti-disturbance performance of the dc-link. Simulations based on MATLAB/Simulink and experimental results obtained from a 75kW prototype validate the correctness and effectiveness of the proposed control scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.