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Bi-Directional Multi-Level Converter for an Energy Storage System

  • Han, Sang-Hyup (Department of Electrical Engineering, Kyungpook National University) ;
  • Kim, Heung-Geun (Department of Electrical Engineering, Kyungpook National University) ;
  • Cha, Honnyong (School of Energy Engineering, Kyungpook National University) ;
  • Chun, Tae-Won (Department of Electrical Engineering, University of Ulsan) ;
  • Nho, Eui-Cheol (Department of Electrical Engineering, Pukyong National University)
  • Received : 2013.10.16
  • Accepted : 2014.02.17
  • Published : 2014.05.20

Abstract

This paper proposes a 3 kW single-phase bi-directional multi-level converter for energy storage applications. The proposed topology is based on the H-bridge structure with four switches connected to the DC-link. A simple phase opposition disposition PWM method that requires only one carrier signal is also suggested. The switching sequence to balance the capacitor voltage is considered. The topology can be extended to a nine-level converter or a three-phase system. The operating principle of the proposed converter is verified through a simulation and an experiment.

Keywords

I. INTRODUCTION

Grid-connected converter systems are increasingly becoming important as a result of the increasing demand on renewable energy [1]-[3]. The prospect of vehicles plugging into electric grids, known as plug-in electric vehicles, reinforces the undeniable economic benefits that result in the independence from petroleum and the displacement of gasoline by electricity. The importance of the trend in future power systems will further intensify. Thus, converters for grid-connected operation should meet the following requirements.

Two-level PWM converters are traditionally used for grid-tied inverter systems. In the case of a two-level converter, the converter switching frequency should be high or the inductance of the output filter inductor has to be sufficient to satisfy the required THD for two-level converters. To address the problems associated with two-level converters, multi-level converters (MLCs) are introduced for grid-connected converters. Several MLC topologies have been suggested. These topologies can be mainly classified into three types, as shown in Fig. 1: neutral point clamped type, flying capacitor type, and cascaded type [4]-[7].

Fig. 1.Topologies of MLC: (a) Neutral point clamped type. (b) Flying capacitor type. (c) Cascaded type.

MLCs are advantageous because their switching frequency and device voltage rating can be significantly lower than those of a traditional two-level converter under the same output voltage. Therefore, switching loss can be reduced significantly, and converter efficiency can be increased [8]-[10].

In this paper, a circuit based on the H-bridge topology with four switches connected to the DC-link is proposed as MLC topology. Fig. 2 shows the proposed MLC. The power flow is bi-directional, and the power factor of the ac side is controllable. The number of the active switches is similar to that of traditional MLCs, as shown in Fig. 1. However, the switches in the H-bridge of the proposed converter (TA+, TA-, TB+ , and TB-) are turned on and off once at the fundamental 60/50 Hz frequency. The voltage stress the switches in the H-bridge is twice the number of switches in the DC-link (TP+, TP-, TN+, and TN-). Thus, a relatively slow and high voltage rating switch is used in the H-bridge, and a fast and low voltage rating switch is used in the DC-link.

Fig. 2.Proposed grid-connected bi-directional multi-level converter for application to the energy storage system.

 

II. OPERATING PRINCIPLE OF THE PROPOSED MULTI-LEVEL CONVERTER

A. Topology of Multi-Level Converter

The proposed MLC is composed of two DC-link capacitors (C1, C2) and four switching devices (TA+, TA-, TB+, TB-) for the H-bridge, as well as four active switches (TP+, TP-, TN+, TN-) located between the DC-link and the H-bridge, as shown in Fig. 2. The voltage across the switching devices in the DC-link is VDC/2. These devices are switched at switching frequency. Meanwhile, the voltage across the switching devices in the H-bridge is VDC. These devices are switched at a frequency of the fundamental component of the output voltage (e.g., 50 or 60 Hz).

Thus, the switches in the DC-link and the H-bridge can be strategically selected based on the rated power of the converter system to reduce system cost and increase efficiency. Table I shows the output voltage according to the switching states.

TABLE IOUTPUT VOLTAGES ACCORDING TO SWITCHING STATES

B. Operating Modes and the Proposed PWM Strategy

The output voltage of the proposed MLC shown in Fig. 2 consists of five levels (VDC, VDC/2, 0, -VDC/2, and -VDC) based on the switching states of the converter. The four operating modes depend on the instantaneous value of the reference voltage and the maximum value of the carrier signal. Table II shows the possible converter output voltage levels according to the operating modes.

TABLE IIOPERATING MODES OF THE PROPOSED MLC

For the N-level NPC type multi-level converter, (N-1) triangular carrier signals with the same frequency and amplitude are used to occupy contiguous bands that range from +VDC to -VDC. A single sinusoidal reference signal is compared with each carrier signal to determine the output voltage for the converter. Three dispositions of the carrier signal are considered in generating the PWM signal [11]-[13].

Fig. 3 shows the reference and carrier signal arrangements for PD, APOD, and POD modulations.

Fig. 3.Carrier and reference signal arrangements for: (a) Phase disposition (PD). (b) Alternative phase opposition disposition (APOD). (c) Phase opposition disposition (POD).

A new PWM strategy based on POD modulation that requires only one carrier signal ( vcarrier ) is proposed. The detailed PWM strategy is depicted in Fig. 4. If the reference signal is positive, then the switch pair (TA+, TB-) is turned on; otherwise, the switch pair (TA-, TB+) is turned on. Thus, the switches comprising the H-bridge converter are turned on and off once during the reference signal period. The voltage across the switch in the H-bridge at the blocking state is VDC. The switches (TP-, TN+) are operated complementarily to the switches (TP+, TN-).

Fig. 4.PWM strategy based on a POD with a single carrier signal.

The generation of the PWM signal for the DC link switches can be explained as follows:

Mode 1: a signal subtracted from the reference signal by Vc is compared with the carrier signal. If (vref -Vc)> vcarrier, then TP+ and TN- are turned on. If (vref -Vc)< vcarrier, then the switch TP+ or TN- is alternately turned off.

Mode 2: the reference signal is directly compared with a carrier signal. If vref > vcarrier, then the switch TP+ or TN- is alternately turned on. If vref < vcarrier, then the switches TP+ and TN- are turned off.

Mode 3: -vref is directly compared with a carrier signal. If -vref > vcarrier, then the switch TP+ or TN- is alternately turned on. If -vref < vcarrier, then the switches TP+ and TN- are turned off.

Mode 4: a signal subtracted from -vref by Vc is compared with the carrier signal. If (-vref -Vc)> vcarrier, then the switches TP+ and TN- are turned on. If (-vref -Vc)< vcarrier, then the switch TP+ or TN- is alternately turned off.

The proposed PWM method is simple because only one carrier signal is used to generate four PWM signals.

C. Voltage Balancing of the DC-Link Capacitor

One of the important issues on MLC is the voltage balance of the DC-link capacitor [14], [15]. The voltage across capacitors C1 and C2 should be equally balanced to VDC/2. However, the midpoint voltage fluctuates when C1 and C2 continuously charge and discharge. If the capacitor voltage is unbalanced, the output voltage becomes asymmetrical, resulting in a high harmonic content in the grid current.

To solve this problem, the switching state should be selected appropriately, as shown in Fig. 5. If only one switch in the DC-link is turned on, the output voltage becomes VDC/2. The DC-link switches (TP+, TN-) are alternately turned on at mode 2 and alternately turned off at mode 1 to balance the DC-link capacitor voltage. The switches (TP-, TN+) are operated complementarily to the switches (TP+, TN-). Therefore, the switching sequences of modes 1 and 2 are (a)-(b)-(a)-(c) and (b)-(d)-(c)-(d), respectively. The switching sequences of modes 3 and 4 are similar to those of modes 1 and 2.

Fig. 5Switching states of the proposed converter in a positive half cycle: (a) state 1 : vAB = VDC. (b) state 2 : vAB = VDC/2. (c) state 3 : vAB = VDC/2. (d) state 4 : vAB = 0.

D. Control Strategy

Fig. 6 shows the block diagram of the current control. A proportional-resonant (PR) controller with a stationary frame is used for the current controller. If the DC-link voltage is controlled by a proportional-integral controller, the voltage controller output can be treated as the active power reference. Thus, if the reactive power reference is given, then the grid current reference can be calculated as follows:

, where Is* =P* / (Vs cosϕ* ), ϕ* = tan-1(Q* / P* ) .

Fig. 6.Block diagram of current control.

The PR controller is a good candidate for reference tracking in a stationary frame because the grid current, which is the control object of the current controller, is a fixed frequency AC (50 or 60 Hz). No steady state error is required and transforming the axes is unnecessary because the gain of the PR controller at a selected resonant frequency is infinite [16], [17].

E. Extensions for the Nine-Level and Three-Phase Five-Level Converters

Notably, although the number of the switching devices in the proposed five-level converter is the same as that of the conventional cascaded H-bridge MLC, the switches in the H-bridge of the proposed MLC are switched at a low frequency (60 Hz). Moreover, unlike the cascaded H-bridge MLC, the proposed five-level inverter requires only one isolated voltage source, VDC.

A nine-level converter, which is extended from the five-level converter shown in Fig. 2, is proposed in this paper to maximize the effectiveness of the proposed MLC. The overall circuit diagram is shown in Fig. 7. As shown in Fig. 7, the proposed converter requires 12 active devices for the nine-level converter, but 16 active devices are required for the cascaded H-bridge MLC. Therefore, the number of switching devices in the proposed MLC can be reduced significantly as the number of voltage level increases.

Fig. 7.Proposed 9-level converter topology.

Fig. 8.Proposed three-phase five-level converter topology.

A unit cell can be produced as a module and the extension of the output voltage level is achieved simply by connecting the modules in a series. The construction of the three-phase multi-level converter is also possible.

 

III. SIMULATION RESULTS

The proposed 3 kVA, five-level converter is simulated to verify the operating principle. The L filter is inserted between the output of the converter and the grid. The electrical specification of the proposed converter is summarized in Table III. Fig. 9 shows the waveforms of the proposed five-level converter. The grid current is satisfactorily controlled in the discharging [Figs. 9(b) to 9(d)] and charging modes [Fig. 9(e)], and the power factor can also be controlled.

TABLE IIIELECTRICAL SPECIFICATION OF THE PROPOSED SINGLE-PHASE FIVE-LEVEL CONVERTER

Fig. 9.Waveforms of the 5-level converter.

 

IV. EXPERIMENTAL RESULTS

Fig. 10 shows the grid connected multi-level converter system with the same conditions as the simulation. The voltage at the Point of Common Coupling (PCC) and the current injected to the PCC are measured. The DC link voltage is also sensed. DSP TMS320F2812 is used to implement the current controller and the voltage controller, to obtain the grid voltage phase, and to generate the PWM signals.

Fig. 10.Grid-connected multi-level converter system.

Fig. 11 shows the output waveforms of the proposed converter. With a five-level output voltage, the grid current is satisfactorily controlled during the discharging and charging modes. Only the waveform at unity power factor is shown for the charging mode because the power factor control function is necessary only for the discharging mode. The THD of the output current is 3.8 %.

Fig. 11.Experimental waveforms of the proposed converter.

 

V. CONCLUSIONS

This paper proposed a new multi-level converter topology based on an H-bridge converter with four switches connected to the DC-link.

The power semiconductor switching devices that configure the H-bridge circuit in the proposed multi-level converter are only responsible for the polarity reversal of the AC output voltage, and the five-level output voltages are generated by the appropriate switching of the DC-link switches. The switching devices in the H-bridge converter are synchronized according to the output voltage signal. Therefore, switching loss is smaller than that of the other converter.

The configuration of the control circuit is simple because the PWM signal is generated by using only one carrier signal. The number of the switching devices in the proposed MLC is fewer than that in the conventional multi-level converter. Thus, the reliability of the proposed system is high, and the cost of the system can be low.

A unit cell can be produced as a module, and extending output voltage level is achieved simply by connecting the module in a series. The construction of the three-phase multi-level converter is also possible.

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