• 한국초전도학회:학술대회논문집
• /
• v.10
• /
• pp.160-164
• /
• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.43-52
• /
• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Progress in Superconductivity
• /
• v.3 no.2
• /
• pp.172-177
• /
• 2002

Superconductive digital to analog converters (DAC) based on Josephson effect produce the voltage steps with high precision and good stability Therefore, they can be applied to obtain a very accurate ac voltage standard. In this paper, we made a simulation study of Rapid Single Flux Quantum (RSFQ) DAC. RSFQ DAC was composed of Non-destructive Head Out (NDRO) cells, T flip-flops, D flip-flops, Splitters, and Confluence Buffers. Confluence Buffer was used in resetting the DACs. We also obtained operating margins of the important circuit parameters in simulations.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.43-53
• /
• 2002

In this paper, a new dynamic D-flip-flop which does not suffer from charge sharing and glitch problems is proposed. And a dual-modulus divide-by-128/129 prescaler has been designed with the proposed D-flip-flops using a 0.6$0.6{\mu}m$ CMOS technology. Eleven-transistor architecture enables it to operate at the higher frequency range and the transistor merging technique contributes to the reduction of power consumption. At 5V supply voltage, the simulated maximum operating frequency and the current consumption of the divide-by-128/129 prescaler are 1.97GHz and 7.453mA, respectively.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.52 no.2
• /
• pp.93-101
• /
• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• Journal of information and communication convergence engineering
• /
• v.5 no.2
• /
• pp.112-115
• /
• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.

• Journal of Sensor Science and Technology
• /
• v.33 no.3
• /
• pp.134-138
• /
• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Progress in Superconductivity
• /
• v.4 no.1
• /
• pp.37-41
• /
• 2002

In this work. we have designed two different kinds of Rapid Single Flux Quantum (RSFQ) OR-gates. One was based on the already developed RSFQ cells and the other was aimed to develop a more compact version. In the first circuit, we used a combination of two D Flip-Flops and a merger and in the other circuit we used a combination of RS Flip-Flops and Confluence Buffer. We tested the circuit performance by using the simulation tools, Xic and Wrspice. We obtained the operation margins of the circuit elements by a margin calculation program, and we obtained the minimum operation margins of $\pm$30%. The circuits were laid out, aimed to fabricate by using the existing KRISS Nb process. KRISS Nb process includes the $Nb／Al_2$$O_3$／Nb trilayer fabricated by DC magnetron sputtering and the reactive ion etching technique for the definition of the features. The major tools used in the layouts were Xic and L-meter.

• Journal of Korea Society of Industrial Information Systems
• /
• v.19 no.6
• /
• pp.33-41
• /
• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Journal of IKEEE
• /
• v.9 no.2 s.17
• /
• pp.152-160
• /
• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.