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A New Dynamic D-Flip-flop for Charge-Sharing and Glitch Reduction  

Yang, Sung-Hyun (Dept. of Computer and Communication Engineering, Chungbuk National University)
Min, Kyoung-Chul (Mtekvision Co. Ltd.)
Cho, Kyoung-Rok (Dept. of Computer and Communication Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.4, 2002 , pp. 43-53 More about this Journal
Abstract
In this paper, a new dynamic D-flip-flop which does not suffer from charge sharing and glitch problems is proposed. And a dual-modulus divide-by-128/129 prescaler has been designed with the proposed D-flip-flops using a 0.6$0.6{\mu}m$ CMOS technology. Eleven-transistor architecture enables it to operate at the higher frequency range and the transistor merging technique contributes to the reduction of power consumption. At 5V supply voltage, the simulated maximum operating frequency and the current consumption of the divide-by-128/129 prescaler are 1.97GHz and 7.453mA, respectively.
Keywords
Flip-flops; prescalers; high-speed circuits; low-power circuits;
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Times Cited By KSCI : 1  (Citation Analysis)
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