• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.668-671
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• 2003

A concept of deadlock point of fuzzy sequential circuit is proposed. There are six cases of fuzzy sequential circuits of 1 state and 1 input variables with deadlock points. Examples of each case are shown both in a form of characteristic equation and in a graphical illustration. As fuzzy sequential circuit with 1 state and 1 input variables, D and T fuzzy flip-Hops are also characterized using the proposed concept. Thus one of the four types of D fuzzy Hip-Hops and T fuzzy Hip-flop have a deadlock point 1/2.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.240-243
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• 1999

This paper presents a data-dependent precharge suppression(DPS) D-flip-flop(DFF) with precharge suppression scheme according to data-transition probability The main feature of the DPS DFF is that precharge is suppressed when there is no data transition. The proposed DPS DFF consumes less power than the conventional Yuan-Svensson's true single phase clocking(TSPC) DFF when the data-transition probability is low. The simulation result shows that the power consumption is reduced by 42.2 % when the data-transition probability is 30%.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.4
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• pp.1-6
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• 1975

본 논문은 Platen동작제어에 의한 한글델레타이프외 세가지 제어논리회로를 설계검토하였다. 일반적인 논리회로 구성방법에 의한 설계결과, 상태, 상태변이함수 그리고 출력함수외 순서로 설계한 Pulse mode의 제어회로가 가장 간단하였다. 이때 필요한 기억소자는 D Flip-Flop 2회 뿐이었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.68-74
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• 1985

In this Paper, we present a non-doglegging channel routing system for If layout using standard cells. This system produces a final two-layer wiring pattern in the horizontal track between two rows, each of which is a linear placement of standard cells of identical heights, satisfying the given net list specification. The layout of CMOS cell library Including nine primitive cells used in this paper is represented in CIF (Caltech Intermediate Form) using λ(Lambda) of 2 microns in Mead-Conway layout representation scheme. The cell dimension and 1/0 characteristics such as name, position and layer type of the pins are stored in Component Library to be used in the channel routing progranl, CROUT. 4 subprogram, NET-PLOT, was used to report a schemdtic layout result, and another subprogram, NETCIF was used to with a full-fledged final layout representation in GIF, A test run for realizing a dynamicmaster-slave D flip-flop with set/reset using primitive cells was shown to take 4 CPU seconds on VAX 11/780.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• The Journal of Korean Association of Computer Education
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• v.22 no.5
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• pp.27-37
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• 2019

In this study, for the purpose of reflection level analysis of high school students in HW design learning which is based on online simulation, we carried out 5 lessons of HW learning and analyzed there reflection levels for 5 individual time of reflection content. The reflection level analysis results for each time of learning shows that the reflection level of the $3^{rd}$ time learning of D-Flip Flop is the highest score with 1.23. The correlation analysis result between the reflection contents presents that high positive correlation between learning content and task resolving method(r=.781, p<.01), and negative design correlation between task resolving method and alternative resolving method. The HW learning satisfaction survey result shows 4.2, and most of the participant students provided opinions that the HW design learning is required and current learning contents is a bit difficult to follow. We could recognize HW design learning is required to have composition of curriculum with basic and advanced contents, and on-off lines combined.