• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.843-850
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• 2016

In this paper, we propose a digital controller design process for the interleaved type of a boost PFC (Power Factor Correction) converter which can disperse the heat of the switching devices due to the interleaved topology. We establish a mathematical model of a boost PFC converter and propose a controller design method based on the root locus. The performance of the designed controller is verified by simulations. The measurement of the input voltage, inductor currents, and the converter output link voltage are needed for the control of the converter system which consists of a power unit and a control unit where a high-performance 32-bit microcontroller is used. The adjustment of A/D conversion timing is also needed to avoid high frequency noise generated when the switches on/off. It is illustrated by the real experiments that the designed control system with the properly adjusted ADC timing satisfies the given performance specifications of the interleaved boost PFC converter in the on-board slow battery charger.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.630-633
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• 1997

This paper describes a design of a single phase PWM converter for high speed train. Parallel operation and control method of four Quadrant PWM converters are described. Simulation and modelling of the converters is performed. Capacity of the converter/inverter and power circuit for high speed traction system designed. And harmonic contents of AC line current's are analyzed. The results of the simulation are presented.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.8
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• pp.893-901
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• 1992

In this paper, we propose a new resolver-to digital(R/D) conversion method, in which a bang-bang type phase comparator is employed for fast tracking. We eliminate from the R/D conversion loop the low-pass filter which is needed to reject carrier signal and noise. Instead, we employ two prefilters outside the R/D conversion loop that take the role of the low-pass filter. Thereby, we can construct a fast and accurate tracking R/D converter. Some simulation and experimental results as well as mathematical performance analysis are presented to demonstrate the superior tracking performance of our R/D converter over conventional tracking R/D converters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.187-191
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• 2007

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2411-2413
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• 1998

In this paper, using tile concept of block digital filtering, and the design procedure of time-interleaved oversampling converter are presented. it is shown that arbitrary sigma-delta A/D converter can be converted into corresponding time-interleaved structure. The TIM structure of this paper is designed by the bilinear transform. To verify the simulation results, a second-order TIM structure A/D converter has been implemented and the design process as well as experimented results are presented.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.534-537
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• 2001

This paper deals with the active clamp ZVS flyback converter for RF generator. The proposed converter has the characteristics of the low switching noise and high efficient regarding conventional flyback converter. To verify validity of the proposed converter, the 100kHz, 48V, 300W converter are simulation and experimental result. This converter will be apply to the discharge drive circuit for PDP(Plasma Display Panel) TV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.