• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.43-49
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• 2004

In this paper, we have designed a mode size converter to reduce coupling loss between super-high delta silica optical waveguides and single mode fibers. The new mode size converter has three design aspects; periodically segmented taper waveguide for minimal size, lateral taper waveguide for simple fabrication, and surrounding trenches to improve coupling loss. In the optimal mode size converter design, coupling loss is 0.33dB/point without trenches and 0.2dB/point with trenches.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.380-387
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• 2002

In this paper, the effect of the phase noise of a local oscillator on the ACPR of a transmitter and the reception sensitivity of a receiver to meet the TIA/EIA/IS-98-D for the CDMA mobile station was analyzed. And the optimum condition for performance of the local oscillator was suggested. It was found that the phase noise level of the local oscillator in a receiver and a transmitter should be below -138.3dBc/Hz and -120dBc/Hz, respectively, at 900kHz offset. It was confirmed that the reception sensitivity and ACPR efficiency were satisfactory when the signal of the local oscillator to the down-converter of a receiver with the phase noise level of less than -138.3dBc/Hz is supplied to the up-converter of the transmitter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1878-1879
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• 2011

주로 사용하는 3상 교류 전동기는 3상의 전압, 전류가 인가되며, 이 3상인 a, b, c상 변수들을 변환하여 d. q, 0축으로 이루어진 직교 좌표계상의 변수로 변환하는 것을 좌표 변환 이라고 하며 통상적으로 교류기의 모델링 또는 해석 시 이 방식을 통하여 실행한다. 기본적으로 좌표 변환 즉 d - q변환은 사용하나 그 이후에 d축과 q축의 전류와 자속쇄교수 구해가는 방식과 d축과 q축을 해석하는 관점의 변화에 따라 모델링에 사용되는 수식이 변환하며 이러한 수식들을 활용하여 모델링을 함으로써 서로의 장단점을 비교하며, 그 비교를 통하여 교류기에 이론적으로 더 근접하고 단순화된 모델링에 대해 연구했다. 그래서 본론에서는 3가지 모델링을 비교한다. 각각의 모델링마다의 장점과 단점이 있으며 그러한 장단점을 비교하여 교류기에 더 근접한 모델링을 결정했다.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1250-1259
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• 2012

In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-${\mu}m$ 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 ${\mu}W$ and 0.126 mm2, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.