• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.414-422
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• 2008

Adsorption experiments for $H_2$, $CH_4$, CO, $CO_2$ on activated carbon and zeolite 5A were performed by static volumetric method. A 4-bed pressure swing adsorption (PSA) process was to study separation of hydrogen from multi-component mixture gases ($H_2$ 72.2%, $CH_4$ 4.06%, CO 2.03%, $CO_2$ 21.6%). Dual-site langmuir (DSL) isotherm showed good or fair agreement with the experimental results. The optimum height of activated carbon layer was 55 cm with breakthrough results on the packing ratio of activated carbon to zeolite 5A. In PSA process, the effects of the process parameters such as total cycle time ($T_c$), ${\Delta}P$ at the provide purge step and adsorption pressure on the PSA performance were studied experimentally and theoretically.

• Korean journal of applied entomology
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• v.58 no.4
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• pp.347-354
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• 2019

Temperature-dependent traits of Laodelphax striatellus, rice stripe virus vector, were investigated at 10 constant temperatures (12.5, 15.0, 17.5, 20.0, 22.5, 25.0, 27.5, 30.0, 32.5, and 35.0 ± 1℃) under a fixed photoperiod (14/10-hr light/dark cycle). Unit functions for the oviposition model were estimated and implemented into a population dynamics model using DYMEX. The longevity of L. striatellus adults decreased with increasing temperature (56.0 days at 15.0℃ and 17.7 days at 35.0℃). The highest total fecundity (515.9 eggs/female) was observed at 22.5℃, while the lowest (18.6 eggs/female) was observed at 35.0℃. Adult developmental rates, temperature-dependent fecundity, age-specific mortality rates, and age-specific cumulative oviposition rates were estimated. All unit equations described adult performances of L. striatellus accurately (r² =0.94~0.97). After inoculating adults, the constructed model was tested under pot and field conditions using the rice-plant hopper system. The model output and observed data were similar up to 30 days after inoculation; however, there were large discrepancies between observed and estimated population density after 30 days, especially for 1^st and 2^nd instar nymph densities. Model estimates were one or two nymphal stages faster than was observed. Further refinement of the model created in this study could provide realistic forecasting of this important rice pest.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.16 no.4
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• pp.155-168
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• 2011

Coastal boundary current flows along the eastern boundary of the Yellow Sea and its speed was about 0.l m/s during the summer 2007. In order to find major factors that affect the coastal boundary current in the eastern Yellow Sea, three-dimensional numerical model experiments were performed. The model simulation results were validated against hydrographic and current meter data in the eastern Yellow Sea. The eastern boundary current flows along the bottom front over the upper part of slopping bottom. Strength and position of the current were affected by tides, winds, local river discharge, and solar radiation. Tidal stirring and surface wind mixing were major factors that control the summertime boundary currents along the bottom front. Tidal stirring was essential to generate the bottom temperature front and boundary current. Wind mixing made the boundary current wider and augmented its north-ward transport. Buoyancy forcing from the freshwater input and solar radiation also affected the boundary current but their contributions were minor. Strong (weak) tidal mixing during spring (neap) tides made the northward transport larger (smaller) in the numerical simulations. But offshore position of the eastern boundary current's major axis was not apparently changed by the spring-neap cycle in the mid-eastern Yellow Sea due to strong summer stratification. The mean position of coastal boundary current varied due to variations in the level of wind mixing.

• Journal of Korean Society of Transportation
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• v.22 no.7 s.78
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• pp.131-137
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• 2004

Conventional traffic signal optimization models assume that green intervals for pedestrian crossings are given as exogenous inputs such as minimum green intervals for straight-ahead movements. As the result, in reality, the green intervals of traffic movements may not distribute adequately by the volume/saturation-flow of them. In this paper, we proposed signal optimization models formulated in BMILP to integrate pedestrian crossings into traffic movements under under-saturated traffic flow. The model simultaneously optimizes traffic and pedestrian movements to minimize weighted queues of primary queues during red interval and secondary queues during queue clearance time. A set of linear objective function and constraints set up to ensure the conditions with respect to pedestrian and traffic maneuvers. Numerical examples are given by pedestrian green intervals and the number of pedestrian crossings located at an arm. Optimization results illustrated that pedestrian green intervals using proposed models are greater than those using TRANSYT-7F, but opposite in the ratios of pedestrian green intervals to the cycle lengths. The simulation results show that proposed models are superior to TRANSYT-7F in reducing delay, where the longer the pedestrian green interval the greater the effect.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.23-35
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• 2011

The pedestrian green time is usually long at wide width intersections. This sometimes causes the increase of delay on the whole intersection because of long cycle length and thus small g/C ratio on some direction. In this paper, to improve these problems, staggered pedestrian crossing was evaluated on the vehicular and pedestrian aspects. The results were gained by using both TRANSYT-7F and VISSIM model. The vehicle control delay of the staggered pedestrian crossing was estimated to be decreasing than that of the general pedestrian crossing by 14.9% to 85.6%. The pedestrian average delay of two pedestrian crossing systems was examined by analytical method and VISSIM. According to the analytical method there was no significant difference between each pedestrian crossing system. The pedestrian delay of staggered pedestrian crossing was from 13.4% to 22.3% than the general pedestrian crossing by VISSIM. In conclusion, the staggered pedestrian crossing was more effective than general pedestrian crossing for both the vehicle and the pedestrian. However this conclusion was resulted from micro simulation where traffic volume condition, v/c, was from 0.8 to 1.1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of Korea Water Resources Association
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• v.39 no.10 s.171
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• pp.823-832
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• 2006

Precipitation is the most important component to the study of water and energy cycle in hydrology. In this study we investigate rainfall retrieval uncertainty from different sources of remotely sensed precipitation field and then probable error propagation in the simulation of hydrologic variables especially, runoff on different vegetation cover. Two remotely sensed rainfall retrievals (space-borne IR-only and ground radar rainfall) are explored and compared visually and statistically. Then, an offline Community Land Model (CLM) is forced with in situ meteorological data to simulate the amount of runoff and determine their impact on model predictions. A fundamental assumption made in this study is that CLM can adequately represent the physical land surface processes. Results show there are big differences between different sources of precipitation fields in terms of the magnitude and temporal variability. The study provides some intuitions on the uncertainty of hydrologic prediction via the interaction between the land surface and near atmosphere fluxes in the modelling approach. Eventually it will contribute to the understanding of water resources redistribution to the climate change in Korean Peninsula.