• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.26-28
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• 1996

A high power SiGe HBT has been fabricated using APCVD(Atmospheric Pressure Chemical Vapor Deposition) and its perfermanoe has been analysed. The composition of Ge in the SiGe base was graded from 0% at the emitter-base junction to 20% at the base-collector junction. As a base electrode, titanium disilicide(TiSi$_2$) was used to reduce the extrinsic base resistance. The SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0GHz and a maximun oscillation frequency(f$_{max}$) of 16.1GHz with a pad de-embedding. The packaged high power SiGe HBT with an emitter area of 2xBx80${\mu}{\textrm}{m}$$^2$typically shows a cutoff frequency of 4.7GHz and a maximun oscillation frequency of 7.1GHz at Ic of 115mA.A.A.

• 센서학회지
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• 제30권6호
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Journal of information and communication convergence engineering
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• 제14권1호
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• pp.35-39
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• 2016

In this paper, we develop a 94-GHz single balanced mixer with low conversion loss using planar Schottky diodes on a GaAs substrate. The GaAs Schottky diode has a nanoscale anode with a T-shaped disk that can yield high cutoff frequency characteristics. The fabricated Schottky diode with an anode diameter of 500 nm has a series resistance of 21 Ω, an ideality factor of 1.32, a junction capacitance of 8.03 fF, and a cutoff frequency of 944 GHz. Based on this technology, a 94-GHz single balanced mixer was constructed. The fabricated mixer shows an average conversion loss of -7.58 dB at an RF frequency of 92.5 GHz to 95 GHz and an IF frequency of 500 MHz with an LO power of 7 dBm. The RF-to-LO isolation characteristics were greater than -32 dB. These values are considered to be attributed to superior Schottky diode characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.840-843
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• 2001

In this study, temperature dependency of current gain for AlGaAs/GaAs/GaAs HBT is analytically proposed over the temperature range between 300K and 600K. Energy bandgap, effective mass, intrinsic carrier concentration are considered as temperature dependent parameters. Collector current which is numerically calculated is then analytically expressed to enhance the speed of calculation for current gain. From the results, current gain decreases as the temperature increases. These results will be used to expect the unity current gain frequency f$_{T}$ in conjunction with emitter-base and collector- base capacitances.s.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.107-112
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• 2011

This paper is for improving the RF frequency performance of a fabricated 100nm ${\Gamma}$-gate MHEMT, scaling down vertically for the epitaxy-structure layers of the device. Hydrodynamic simulation parameters are calibrated for the fabricated MHEMT with the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure grown on the GaAs substrate. With these calibrated parameters, simulations for the vertically-scaled epitaxial layers of the device are performed and analyzed for DC/RF characteristics, including the quantization effect due to the thickness reduction of InGaAs channel layer. A newly designed epitaxy-structure device shows higher extrinsic transconductance, $g_m$ of 1.556 S/mm, and higher frequency performance, $f_T$ of 222.5 GHz and $f_{max}$ of 849.6 GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.77-80
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• 2002

In this paper, InP-based HBTs have been optimally designed by numerical simulation and fabricated by the self-aligned process. The structure of HBT was designed in terms of the current gain*f$_{max}$ for the base and f$_{T}$*f$_{max}$ for the collector. The designed structure produced the current gain of about 50 and the cutoff frequency and the maximum oscillation frequency of 87GHz and 2940Hz respectively. In addition, we present a study of the vertical and lateral etching of InP with the mask sides parallel to the principal crystallographic axes, [0101 and (001). This etching characteristics arc used to fabricate self-aligned HBT structures with reduced parasitic effects.s.s.s.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 춘계학술대회 논문집
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• pp.236-238
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• 1997

A cellular power amplifier using an APCVD(Atmospheric Pressure Chemical Vapor Deposition)-grown SiGe base HBT of ETRI has been designed with a linear simulation CAD. The Si/SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0 GHz and a maximum oscillation frequency(f$_{max}$) of 16.1 GHz with a pad de-embedding A packaged power Si/SiGe HBT with an emitter area of 2$\times$8$\times$80${\mu}{\textrm}{m}$$^2$typically shows a f$_{T}$ of 4.7 GHz and a f$_{max}$ of 7.1 GHz at a collector current (Ic) of 115 mA. The power amplifier exhibits a Forward transmission coefficient(S21) of 13.5 dB, an input and an output reflection coefficients of -42 dB and -45 dB respectively. Up to now the III-V compound semiconductor devices hale dominated microwave applications, however a rapid progress in Si-based technology make the advent of the Si/SiGe HBT which is promising in low to even higher microwave range because of lower cost and relatively higher reproducibility of a Si-based process.ess.ess.

• 대한전자공학회논문지SD
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• 제40권9호
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• pp.644-650
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• 2003

본 논문은 밀리미터파 대역에서 사용될 PHEMT의 특성향상을 위한 연구의 일원으로 게이트 식각에 따른 소자의 특성 변화를 연구하였다. PHEMT는 ohmic 금속을 리세스 패턴으로 사용한 wide 리세스와 게이트 패턴을 리세스 패턴으로 사용한 narrow 리세스의 두가지를 이용하여 제작하였다. 제작된 PHEMT의 최대 전달컨덕턴스(g/sub m/)는 wide 리세스를 이용한 경우 332.7 mS/mm, narrow 리세스를 이용한 경우 504.6 mS/mm의 값을 각각 얻었다. 소신호 주파수 특성으로, wide 리세스를 이용하여 제작한 PHEMT는 전류 이득 차단주파수(f/sub T/) 113 GHz, 최대 공진 주파수(f/sub max/) 172 GHz를 각각 얻었다. Narrow 리세스를 이용하여 제작한 PHEMT의 전류 이득 차단주파수(f/sub T/)와 최대 공진 주파수(f/sub max/)는 101 GHz, 142 GHz를 각각 얻었다. 측정된 결과는 소신호 모델에서 각 파라미터의 변화와 비교, 분석하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.