• 제목/요약/키워드: Current on/off ratio

검색결과 358건 처리시간 0.034초

ON/OFF 전류비를 향상시킨 새로운 bottom-gate 구조의 다결정 실리콘 박막 트랜지스터 (A Novel Bottom-Gate Poly-Si Thin Film Transistors with High ON/OFF Current Ratio)

  • 전재홍;최권영;박기찬;한민구
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제48권5호
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    • pp.315-318
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    • 1999
  • We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

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Ar Ion Beam 처리를 통한 Organic Thin Film Transistor의 성능향상 (Performance enhancement of Organic Thin Film Transistor by Ar Ion Beam treatment)

  • 정석모;박재영;이문석
    • 대한전자공학회논문지SD
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    • 제44권11호
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    • pp.15-19
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    • 2007
  • OTFTs (Organic Thin Film Transistors)의 구동에 있어, 게이트 절연막 표면과 채널의 계면상태가 소자의 전기적 특성에 큰 영향을 미치게 된다. OTS(Octadecyltrichlorosilane)등과 같은 습식 SAM(Self Assembly Monolayer)를 이용하거나, $O_2$ Plasma와 같은 건식 표면 처리등 여러 표면 처리법에 대한 연구가 진행되고 있다. 본 논문에서는 pentacene을 진공 증착하기 전에 게이트 절연막을 $O_2$ plasma와 Ar ion beam을 이용하여 건식법으로 전처리 한 후 표면 특성을 atomic force microscope (AFM) and X-ray photoelectron spectroscopy (XPS)를 사용하여 비교 분석하였고, 각 조건으로 OTFT를 제작하여 전기적 특성을 확인하였다. Ar ion beam으로 표면처리 했을 때, $O_2$ plasma처리했을 때 보다 향상된 on/off ratio 전기적 특성을 얻을 수 있었다. 표면 세정을 위하여 $O_2$ plasma 처리시 $SiO_2$ 표면의 OH-기와 반응하여 oxide trap density가 높아지게 되고 이로 인하여 off current가 증가하는 문제가 발생한다. 불활성 가스인 Ar ion beam 처리를 할 경우 게이트 절연막의 세정 효과는 유지하면서, $O_2$ Plasma 처리했을 때 증가하게 되는 계면 trap을 억제할 수 있게 되어, mobility 특성은 동등 수준으로 유지하면서 off current를 현저하게 줄일 수 있게 되어, 결과적으로 높은 on/off ratio를 구현할 수 있다는 것을 확인하였다.

Design of a Plasmonic Switch Using Ultrathin Chalcogenide Phase-change Material

  • Lee, Seung-Yeol
    • Current Optics and Photonics
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    • 제1권3호
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    • pp.239-246
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    • 2017
  • A compact plasmonic switching scheme, based on the phase change of a thin-film chalcogenide material ($Ge_2Sb_2Te_5$), is proposed and numerically investigated at optical-communication wavelengths. Surface plasmon polariton modal analysis is conducted for various thicknesses of dielectric and phase-change material layers, and the optimized condition is induced by finding the region of interest that shows a high extinction ratio of surface plasmon polariton modes before and after the phase transition. Full electromagnetic simulations show that multiple reflections inside the active region may conditionally increase the overall efficiency of the on/off ratio at a specific length of the active region. However, it is shown that the optimized geometrical condition, which shows generally large on/off ratio for any length of active region, can be distinguished by observing the multiple-reflection characteristic inside the active region. The proposed scheme shows an on/off switching ratio greater than 30 dB for a length of a few micrometers, which can be potentially applied to integrated active plasmonic systems.

Application of a Pulse Electric Field to Cross-flow Ultrafiltration of Protein Solution

  • Kim, Hyong-Ryul;Lee, Kisay
    • Biotechnology and Bioprocess Engineering:BBE
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    • 제4권1호
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    • pp.46-50
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    • 1999
  • The application of pulsed electric field was investigated in the crossflow ultrafiltration of BSA (bovine serum albumn) to economize the application time of electric current as well as to avoid inherent problems of long-term application of electric field. During the application of various cyclic patterns of pulsed electric current, the averaged filtration flowrate and the degree of concentration were maintained higher than those obtained in the absence of electric current application. The temperature increase, pH change, and BSA loss by electrodeposition were all negligible during the operation. The averaged filtration flowrate increased as the ON/OFF duration ratio of electric current was higher and as the period of ON/OFF cycle was shorter. The re-establishment of concentration polarization was dependent to the duration of current OFF state and, therefore, a longer duration of OFF state was not favorable in maintaining higher filtration flow rate. Although the averaged filtration flowrate was enhanced as the magnitude of electric current increased, the flowrate enhancement became smaller as the magnitude of current value above which the degree of electrokinetic depolarization is no further improved.

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수소화된 비정질규소 박막트랜지스터의 누설전류 (Leakage Current of Hydrogenated Amorphous Silicon Thin-Film Transistors)

  • 이호년
    • 한국산학기술학회논문지
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    • 제8권4호
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    • pp.738-742
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    • 2007
  • 능동형 평판디스플레이 소자를 제작하기 위해 수소화된 비정질 규소 박막트랜지스터 (a-Si:H TFT)의 상부에 화소전극을 형성하는 과정에 따른 TFT의 특성 변화를 연구하였다. 화소전극 형성 전에 1 pA 수준의 오프상태 전류 및 $10^6$ 이상의 스위칭률을 보이던 TFT에 화소전극 공정을 행하면 오프상태 전류가 10 pA 이상으로 증가하여 소자특성이 악화되었다. 이러한 소자특성의 악화는 SiNx 보호막 표면의 플라즈마 처리로 개선될 수 있었는데, 특히 $N_2$ 플라즈마가 좋은 결과를 보였다. 화소전극 공정에 의해서 누설전류가 증가하는 것은 투명전도막 증착공정 중에 SiNx 보호막 표면에 전하가 축적되어 이에 유도되는 백채널의 캐리어 축적에 기인하는 것으로 추정된다.

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스텝 어닐링에 의한 저온 및 고온 n형 다결정 실리콘 박막 트랜지스터의 전기적 특성 분석 (Analysis of Electrical Characteristics of Low Temperature and High Temperature Poly Silicon TFTs(Thin Film Transistors) by Step Annealing)

  • 이진민
    • 한국전기전자재료학회논문지
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    • 제24권7호
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    • pp.525-531
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    • 2011
  • In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

High Performance Bottom Contact Organic TFTs on Plastic for Flexible AMLCD

  • Kim, Sung-Hwan;Choi, Hye-Young;Han, Seung-Hoon;Jang, Jin;Cho, Sang-Mi;Oh, Myung-Hwan
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.889-892
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    • 2004
  • We developed a high performance bottom contact, organic thin-film transistor (OTFT) array on plastic using a self-organized process. The effect of OTS treatment on the PVP gate insulator for the performance of OTFT on plastic has been studied The OTFT without OTS exhibited a field-effect mobility of 0.1 $cm^2$/Vs on/off current ratio of > $10^7$. On the other hand, OTFT with OTS, exhibited a field-effect mobility of 1.3 $cm^2$/Vs and on/off current ratio of>$10^8$.

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낮은 누설전류를 위한 소스/드레인-게이트 비중첩 Nano-CMOS구조 전산모사 (Simulation of nonoverlapped source/drain-to-gate Nano-CMOS for low leakage current)

  • 송승현;이강승;정윤하
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.579-580
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    • 2006
  • Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

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OFF 전류의 감소를 위한 다결정 실리콘 박막 트랜지스터의 구조 연구 (A Study on the Structure of Polycrystalline Silicon Thin Film Transistor for Reducing Off-Current)

  • 오정민;민병혁;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 B
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    • pp.1292-1294
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    • 1993
  • This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

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Effects of Ga Composition Ratio and Annealing Temperature on the Electrical Characteristics of Solution-processed IGZO Thin-film Transistors

  • Lee, Dong-Hee;Park, Sung-Min;Kim, Dae-Kuk;Lim, Yoo-Sung;Yi, Moonsuk
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권2호
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    • pp.163-168
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    • 2014
  • Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of $0.1135cm^2/V{\cdot}s$, ${\sim}10^6$, 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at $300^{\circ}C$, $350^{\circ}C$, and $400^{\circ}C$ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.