• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• Journal of Electrochemical Science and Technology
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• v.11 no.1
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• pp.60-67
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• 2020

In this study, copper (II) oxide powder for electroplating was prepared by recovering CuCl₂ from NaClO₃ type etching wastes via recovered non-sintering two step chemical reaction. In case of alkali copper carbonate [mCuCo₃·nCu(OH)₂], first reaction product, CuCo₃ is produced more than Cu(OH)₂ when the reaction molar ratio of sodium carbonate is low, since m is larger than n. As the reaction molar ratio of sodium carbonate increased, m is larger than n and Cu(OH)₂ was produced more than CuCO₃. In the case of m has same values as n, the optimum reaction mole ratio was 1.44 at the reaction temperature of 80℃ based on the theoretical copper content of 57.5 wt. %. The optimum amount of sodium hydroxide was 120 g at 80℃ for production of copper (II) oxide prepared by using basic copper carbonate product of first reaction. At this time, the yield of copper (II) oxide was 96.6 wt.%. Also, the chloride ion concentration was 9.7 mg/L. The properties of produced copper (II) oxide such as mean particle size, dissolution time for sulfuric acid, and repose angle were 19.5 mm, 64 second, and 34.8°, respectively. As a result of the hole filling test, it was found that the copper oxide (II) prepared with 120 g of sodium hydroxide, the optimum amount of basic hydroxide for copper carbonate, has a hole filling of 11.0 mm, which satisfies the general hole filling management range of 15 mm or less.

• Korean Journal of Metals and Materials
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• v.50 no.2
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.191-191
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• 2015

반도체 소자 성능 향상을 위한 3차원 TSV배선 공정이 연구되었다. 전기도금을 이용한 TSV 공정 시 기존에는 황산 구리 수용액내에 억제제, 가속제, 평탄제등을 첨가한 복잡한 전해질이 사용되었지만 본 연구에서는 억제제만을 이용하여 Cu bottom-up filling에 성공하여 전해질의 조성을 단순화 시켰다.

• Korean Journal of Metals and Materials
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• v.48 no.6
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.179-179
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• 2011

관통전극(TSV, Trough Silicon Via) 기술은 전자부품의 소형화, 고성능화, 생산성 향상을 이룰 수 있는 기술이다. Cu는 현재 배선 기술에 적용되고 있고 전기적 저항이 낮아서 TSV filling 재료로 사용된다. 하지만 확산 방지막에 의해 완벽히 감싸지지 않는다면, Cu+은 빠르게 절연막을 통과하여 Si 웨이퍼로 확산된다. 이런 현상은 절연막의 누설과 소자의 오동작 등의 신뢰성 문제를 일으킬 수 있다. 현재 TSV의 제조와 열 및 기계적 응력에 관한 연구는 활발히 진행되고 있으나 Biased-Thermal Stress(BTS) 조건하의 Cu 확산에 관한 연구는 활발하지 않는 것이 실정이다. 이를 위해 본 연구에서는 TSV용 Cu 확산 방지막 Ti에 대해 Cu+의 drift 억제 특성을 조사하였다. 실험을 위해 Cu/확산 방지막/Thermal oxide/n-type Si의 평판 구조를 제작하였고 확산 방지막의 두께에 따른 영향을 조사하기 위해 Ti의 두께를 10 nm에서 100 nm까지 변화하였으며 기존 Cu 배선 공정에서 사용되는 확산 방지막 Ta와 비교하였다. 그리고 Cu+의 drift 측정을 위해 Biased-Thermal Stress 조건(Thermal stress: $275^{\circ}C$, Bias stress: +2MV/cm)에서 Capacitance 및 Timedependent dielectric breakdown(TDDB)를 측정하였다. 그 결과 Time-To Failure(TTF)를 이용하여 Cu+의 drift를 측정할 수 있었으며, 확산 방지막의 두께가 증가할수록 TTF가 증가하였고 물질에 따라 TTF가 변화하였다. 따라서 평판 구조를 이용한 본 실험의 Cu+의 drift 측정 방법은 향후 TSV 구조에서도 적용 가능한 방법으로 생각된다.

• Korean Journal of Materials Research
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• v.9 no.6
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• pp.583-588
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• 1999

The characteristics of copper thin films and pattern filling capability were investigated by ECD. Prior to deposition of copper film, seed-Cu/Ta(TaN)/$SIO_2$(BPSG)/Si structure was manufactured. Copper deposition was performed with various current waveforms(DC/PC, 1~10,000Hz) and current densities(10~60 mA/$\textrm{cm}^2$) after pretreatment (Oxident removal, wetting) of seed-layer. Conformal pattern filling was performed using PC method with fast deposition rate of 6,000~8,000$\AA$/min. Heat-treated($450^{\circ}C$, 30min) copper films showed good resistivities of 1.8~2.1$\mu$$\Omega$.cm. According to the XRD analysis, (111)-preferred orientation of copper film was found in ECD-Cu/seed-Cu/Ta/$Sio_2$/Si structure. Also, we have successfully achieved to fill via holes with 0.35$\mu\textrm{m}$ width and 4:1 aspect ratio.