• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Clean Technology
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• v.17 no.2
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• pp.103-109
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• 2011

The process optimization was carried out to improve the throwing power (TP) and the thickness uniformity of the electroless copper (Cu) plating, which plays a seed layer for the subsequent electroplating. The DOE (design of experiment) was employed to screen key factors out of all available operation parameters to influence the TP and thickness uniformity the most. It turned out that higher Cu ion concentration and lower plating temperature are advantageous to accomplish uniform via filling and they are accounted for based on the surface reactivity. To visualize what occurred experimentally and evaluate the phenomena qualitatively, the kinetic Monte Carlo (MC) simulation was introduced. The combination of neatly designed experiments by DOE and supporting theoretical simulation is believed to be inspiring in solving similar kinds of problems in the relevant field.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.239-241
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• 2009

DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

• Corrosion Science and Technology
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• v.18 no.2
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• pp.39-48
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• 2019

The feasibility of using benzotriazole (BTAH) to inhibit pitting corrosion in the sprinkler copper tubes was investigated by filling the tubes with BTAH-water solution in 829 households at an eight-year-old apartment complex. The water leakage rate was reduced by approximately 90% following BTAH treatment during 161 days from the previous year. The leakage of one of the two sprinkler copper tubes was investigated with optical microscopy, scanning electron microscopy, energy dispersive spectroscopy, X-ray photoelectron spectroscopy, and X-ray diffraction analysis to determine the formation of Cu-BTA film inside the corrosion pits. All the inner components of the corrosion pits were coated with Cu-BTA films suggesting that BTAH molecules penetrated the corrosion products. The Cu-BTA film was about 2 nm in thickness at the bottom of a corrosion pit. A layer of CuCl and $Cu_2O$ phases lies under the Cu-BTA film. This complex structure effectively prevented the propagation of corrosion pits in the sprinkler copper tubes and reduced the water leakage.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.19-24
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• 2009

Formation of an adhesion/barrier layer and a seed layer by sputtering techniques followed by electroplating has been one of the most widely used methods for the filling of through-Si via (TSV) with high aspect ratio for 3-D packaging. In this research, the adhesion and diffusion-barrier properties of the $TaN_x$ film deposited by reactive sputtering were investigated. The adhesion strength between Cu film and $SiO_2$/Si substrate was quantitatively measured by $180^{\circ}$ peel test and topple test as a function of the composition of the adhesive $TaN_x$ film. As the nitrogen content increased in the adhesive $TaN_x$ film, the adhesion strength between Cu and $SiO_2$/Si substrate increased, which was attributed to the increased formation of interfacial compound layer with the nitrogen flow rate. We also examined the diffusion-barrier properties of the $TaN_x$ films against Cu diffusion and found that it was improved with increasing nitrogen content in the $TaN_x$ film up to N/Ta ratio of 1.4.

• Korean Chemical Engineering Research
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• v.52 no.1
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• pp.26-39
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• 2014

Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.