• Journal of the Microelectronics and Packaging Society
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• v.31 no.1
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• pp.35-42
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• 2024

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.17-24
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• 2008

Thermal annealing and electromigration test were performed at $150^{\circ}C$ and $150^{\circ}C,\;5{\times}10^4\;A/cm^2$ conditions, respectively, in order to compare the growth kinetics of intermetallic compound(IMC) in Cu pillar bump. The quantitative interfacial adhesion energy with annealing was measured by using four-point bending strength test in order to assess the effect of IMC growth on the mechanical reliability of Cu pillar bump. Only $Cu_6Sn_5$ was observed in the Cu pillar/Sn interface after reflow. However, $Cu_3Sn$ formed and grew at Cu pillar/$Cu_6Sn_5$ interface with increasing annealing and stressing time. The growth kinetics of total($Cu_6Sn_5+Cu_3Sn$) IMC changed when all Sn phases in Cu pillar bump were exhausted. The complete consumption time of Sn phase in electromigration condition was faster than that in annealing condition. The quantitative interfacial adhesion energy after 24h at $180^{\circ}C$ was $0.28J/m^2$ while it was $3.37J/m^2$ before annealing. Therefore, the growth of IMC seem to strongly affect the mechanical reliability of Cu pillar bump.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.1-10
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• 2023

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2008.11a
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• pp.28.1-28.1
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• 2008

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.15-20
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• 2012

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.757-758
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• 2011

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.15-20
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• 2007

Growth kinetics of intermetallic compound (IMC) at various interface in Cu pillar bump during aging have been studied by thermal aging at 120, 150 and $165^{\circ}C$ for 300h. In result, $Cu_6Sn_5\;and\;Cu_3Sn$ were observed in the Cu pillar/SnPb interface and IMC growth followed parabolic law with increasing aging temperatures and time. Also, growth kinetics of IMC layer was faster for higher aging temperature with time. Kirkendall void formed at interface between Cu pillar and $Cu_3Sn$ as well as within the $Cu_3Sn$ layer and propagated with increasing time. $(Cu,Ni)_6Sn_5$ formed at interface between SnPb and Ni(P) after reflow and thickness change of $(Cu,Ni)_6Sn_5$ didn't observe with aging time. The apparent activation energies for growth of total $(Cu_6Sn_5+Cu_3Sn),\;Cu_6Sn_5\;and\;Cu_3Sn$ intermetallics from measurement of the IMC thickness with thermal aging temperature and time were 1.53, 1.84 and 0.81 eV, respectively.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.