• Title/Summary/Keyword: Core-Chip

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Design of a Low-Power CMOS Fractional-N Frequency Synthesizer for 2.4GHz ISM Band Applications (2.4GHz ISM 대역 응용을 위한 저전력 CMOS Fractional-N 주파수합성기 설계)

  • Oh, Kun-Chang;Kim, Kyung-Hwan;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.60-67
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    • 2008
  • A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

A Micro Fluxgate Magnetic Sensor with Closed Magnetic Path (폐자로를 형성한 마이크로 플럭스게이트 자기 센서)

  • 최원열;황준식;강명삼;최상언
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.3
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    • pp.19-23
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    • 2002
  • This paper presents a micro fluxgate magnetic sensor in printed circuit board (PCB). In order to observe the effect of the closed magnetic path, the magnetic cores of rectangular-ring and two bars were each fabricated. Each fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ~100,000. Four outer layers as an excitation and pick-up coils have a planar solenoid and are made of copper foil. In case of the fluxgate sensor having the rectangular-ring shaped core, excellent linear response over the range of -100 $\mu$T to + 100 $\mu$T is obtained with 540 V/Tsensitivity at excitation square wave of 3 $V_{p-p}$ and 360 KHz. The chip size of the fabricated sensing element is $7.3 \times 5.7\textrm{mm}^2$. The very low power consumption of ~8 mW was measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.n.

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Design of Built-In-Self-Repair Circuit for Embedded Memory Using 2-D Spare Memory (2차원 여분 메모리를 이용한 내장메모리의 자가치유회로 설계)

  • Choi, Ho-Yong;Seo, Jung-Il;Cha, Sang-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.54-60
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    • 2007
  • This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

An 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC for High-Performance Display Applications (고성능 디스플레이 응용을 위한 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC)

  • In Kyung-Hoon;Kim Se-Won;Cho Young-Jae;Moon Kyoung-Jun;Jee Yong;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.1
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    • pp.47-55
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    • 2005
  • This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

Design and fabrication of paper microfluidic channel (종이기반 미세유체 채널의 설계 및 제작기술)

  • Lee, Jung-Hyun;Hwang, Yoo-Sun;Jung, Hyo-Il
    • Science of Emotion and Sensibility
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    • v.14 no.4
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    • pp.525-530
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    • 2011
  • Emotion is composed of various feelings such as pleasure, sorrow, comfortability, and so on. The complicated process of the measurement has long been recognized as a major hindrance for the studies of emotion. Previously, individuals' emotion has mainly been measured by means of self-report, interview, EEG (electroencephalogram), ECG (electrocardiogram), EOG (electroculography), and body temperature. With thanks to nano/micro technologies, the possibility in the development of emotion-on-a-chip (EOC) has begun to be proposed. EOC will make it possible to analyze one's psychological status by taking a drop of blood. Discovery of emotional biomarkers in body fluids, understanding of the correlation between those biomarkers and the results from brain science are prerequisites to validate the EOC technology. In this paper, paper microfluidics are introduced as a good candidate for the EOC. As paper microfluidics is cost-effective and easy to use it is expected to be a useful device for the emotion measurement. We present the design and fabrication process for the simple paper-based microfluidic device and discuss the possible application in the field of measuring the human emotion.

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Development of Embedded RFID R/W System Using PXA255 ARM Chip (PXA255 ARM칩을 활용한 임베디드 RFID R/W 시스템 개발)

  • Hwang, G.H.;Jang, W.T.;Sim, H.J.
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.43 no.6 s.312
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    • pp.61-67
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    • 2006
  • In this paper it was introduced that embedded RFID Reader /Writer system including PXA255 ARM chip which enables the Tag signal to be used by data and video processing via IEEE 802.11 communication protocol. Embedded RFID R/W middle ware was developed which transmit the searched result in the data base using the received Tag signal via IEEE 802.11 communication protocol. Developed embedded RFID R/W system was composed of three parts - PXA255 ARM chid (Core Part) 13.56 MHz RFID Reader /Writer, wireless LAN for data communication with server and TFT-LCD terminal. Once this system receives the Tag signal through the serial port, it transmits the data through the wireless LAN to the server and it displays the received image data which was processed by the server onto the TFT-LCD screen. Embedded RFID R/W Middle ware transmits the received Tag signal from RFID R/W to the embedded system, which activates the socket program to connect to the window server via IEEE 802.11 communication protocol and transmits the Tag signal. Window server program searches the Database using this Tag information and displays the result on to the TFT-LCD window in the embedded system via IEEE 802.11 protocol.

Fracture Strength of All-Ceramic 3-Unit Fixed Partial Dentures Manufactured by CAD/CAM and Copy-Milling Systems (CAD/CAM 및 카피밀링 시스템을 이용하여 제작한 구치부 3-유닛 고정성 국소의치의 파절강도)

  • Kang, Hoo-Won;Kim, Hee-Jin;Kim, Jang-Ju;Ko, Myung-Won
    • Journal of Technologic Dentistry
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    • v.34 no.2
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    • pp.95-103
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    • 2012
  • Purpose: Fracture strength of all-ceramic 3-unit fixed partial dentures manufactured by CAD/CAM and copy-milling systems were evaluated. Methods: Zirconia cores were made by milling the pre-sintered zirconia block by CAD/CAM or copy milling method followed by subsequent sintering. By building-up the corresponding porcelains on the core, all-ceramic bridges were fabricated, and those were evaluated in comparison with PFM fixed partial denture. Results: During the flexural test of the 3-unit PFM bridge, the porcelain started to chip or break at 507.28(${\pm}62.82$)kgf and the metal framework did not break until the maximum load level of 800kgf which was set in the testing instrument of this study. However, among all-ceramic restoration test groups, Everest(EV) group showed a peeling off or breakage of the porcelain from 365.64(${\pm}64.96$)kgf and the core was broken at 491.77(${\pm}55.62$)kgf. Those values of Zirkonzahn(ZR) were 431.03(${\pm}58.47$)kgf and 602.74(${\pm}48.44$)kgf, respectively. The break strength of the porcelain of PFM(PM) group was significantly higher than that of EV (p<0.05) group and there was no significant difference when comparing to that of ZR (p>0.05). ZR group showed higher break strength than that of EV group however there was no significant difference (p>0.05). The break strength of cores were in the increasing order of EV < ZR < PM (p<0.05). Conclusion: We could find that even though the PM group fractured at much higher value than all-ceramic cores, the breakage values of the porcelain of PM group with crack formation or delamination, which will be regarded as clinical failure, was significantly higher than that of EV group and not significantly higher than that of ZR group at p-values of 0.05. The break strength of ZR group was higher than that of EV group at an insignificant level(p>0.05).

Micro fluxgate magnetic sensor using multi layer PCB process (PCB 다층 적층기술을 이용한 마이크로 플럭스게이트 자기 센서)

  • Choi, Won-Youl;Hwang, Jun-Sik;Choi, Sang-On
    • Journal of Sensor Science and Technology
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    • v.12 no.2
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    • pp.72-78
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    • 2003
  • To observe the effect of excitation coil pitch on the micro fluxgate magnetic sensor, two sensors are fabricated using multi layer board process and the pitch distance of excitation coil are $260\;{\mu}m$ and $520\;{\mu}m$, respectively. The fluxgate sensor consists of five PCB stack layers including one layer of magnetic core and four layers of excitation and pick-up coils. The center layer as magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ${\sim}100,000$ and has a rectangular-ring shape to minimize the magnetic flux leakage. Four outer layers as excitation and pick-up coils have a planar solenoid structure and are made of copper foil. In case of the fluxgate sensor having the excitation coil pitch of $260\;{\mu}m$, excellent linear response over the range of $-100\;{\mu}T$ to $+100\;{\mu}T$ is obtained with sensitivity of 780 V/T at excitation sine wave of $3V_{p_p}$ and 360 kHz. The chip size of the fabricated sensing element is $7.3\;{\times}\;5.7\;mm^2$. The very low power consumption of ${\sim}8\;mW$ is measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.

A Bibliometric Analysis on LED Research (계량서지적 기법을 활용한 LED 핵심 주제영역의 연구 동향 분석)

  • Lee, Jae-Yun;Kim, Pan-Jun;Kang, Dae-Shin;Kim, Hee-Jung;Yu, So-Young;Lee, Woo-Hyoung
    • Journal of Information Management
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    • v.42 no.3
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    • pp.1-26
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    • 2011
  • The domain of LED is analyzed for describing the current status of Korea's R&D in the domain comparing with those of others quantitatively. Fourteen sub-domains of LED manufacturing technology are selected and the time span for analysis is ten-year: 2001-2010. Bibiliometric analysis is performed by the unit of publication, core researcher, institution and country. Strategical diagram is also produced with devised two indicators: NGI and NPI. As a result, Korea is competitive in the area of Chip Scale Package, but R&D supports in another promising areas, such as large-caliber sapphire wafer, are necessary. It is also revealed that research activities are expanded dominantly in academia, but practical technologies are developed in industrial circle. It is suggested that to support core corporate and to encourage industrial-academic collaboration is essential for systematical technology development and high achievement in prominent areas.

Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.64-71
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    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.