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Design of Built-In-Self-Repair Circuit for Embedded Memory Using 2-D Spare Memory  

Choi, Ho-Yong (School of Electrical and Computer Eng. Chungbuk National University)
Seo, Jung-Il (SiliconWorks Co.)
Cha, Sang-Rok (Dept. of Semiconductor Eng. Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.12, 2007 , pp. 54-60 More about this Journal
Abstract
This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.
Keywords
Built-In-Self-Repair; Built-In-Self-Test; Spare Memory; Embedded Memory;
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