• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.9
• /
• pp.47-54
• /
• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• 전자공학회논문지 IE
• /
• v.48 no.2
• /
• pp.6-11
• /
• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.866-869
• /
• 2015

With the advance in semiconductor technology, the number of elements that can be integrated in system-on-chip(SoC) increases exponentially, and thus voltage scaling is indispensable to enhance energy efficiency. Near-threshold voltage computing(NTC) improves the energy efficiency by an order of degree, hence it is able to overcome the limitation of conventional super-threshold voltage computing(STC). Although NTC-based low performance manycore system can be used to maximize energy efficiency, it demands more number of cores to sustain the performance, which results in considerable increase of area. In this paper, we analyze NTC manycore architecture considering the trade-offs between performance, power, and area. Therefore, we propose an algorithmic methodology that can optimize power consumption and area while satisfying the required performance by determining the constrained number of cores and size of caches and clusters in NTC environment. Experimental results show that proposed NTC architecture can reduce power consumption by approximately 16.5 % while maintaining the performance of STC core under area constraint.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.7
• /
• pp.122-129
• /
• 2014

Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.7
• /
• pp.1-12
• /
• 2014

This paper is proposed to design the new heat-sink apparatus for improving the heat transfer characteristics in the power LED chip, and results of the operation characteristics were discussed. The core design is that the soldering through-hole on the FR-4 PCB board is formed to the effective heat transfer. That is directly filled with Ag-nano materials, which shows the high thermal conductivity. The heat transfer medium consisting of Ag-nano materials is classified into two structures. Mediums are called as the heat slug and the multi-pin in this work. The heat of the high temperature generated from the LED chip was directly transferred to the heat slug of the one large size. And the accumulated heat from the heat slug was quickly dissipated by the medium of the multi-pin, which is the same body with the heat slug. This multi-pin was designed for the multi-dissipation of heat by increasing the surface areas with a little pins. Subsequently, the speed of the heat transfer with this new heat-sink apparatus is three times faster than the conventional heat-sink. Therefore, the efficiency of the illuminating light will be improved by adapting this new heat-sink apparatus in the large area's LED.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.124-130
• /
• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.3
• /
• pp.699-707
• /
• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.137-147
• /
• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.31-38
• /
• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Korean Magnetics Society
• /
• v.18 no.2
• /
• pp.58-62
• /
• 2008

$Ni_{0.4}Zn_{0.4}Cu_{0.2}Fe_2O_4$ ferrite was fabricated by solid stat reaction method and sol-gel method. Because of the drawbacks of each method, we combined these two methods together. We proposed and experimentally verified that nanocrystalline ferrite additive was effective on improving the densification behavior and magnetic properties of NiZnCu ferrites for multilayer chip inductors. The initial permeability of the toroidal core Sample with 20 wt% nanocrystalline ferrite increased from 78.1 to 178.2 as annealing temperature is increased from $880^{\circ}C$ to $920^{\circ}C$. The density, shrinkage and saturation magnetization were increased with increasing annealing temperature, which was attributed to the decrease of additive grain size and increase of sintering density.