1 |
T. Chen and S. Naffziger, "Comparison of Adaptive Body Bias and Adaptive Supply Voltage for Improving Delay and Leakage under the Presence of Process Variation," IEEE Transaction on very large scale integration systems, Vol. 11, No. 5, pp. 888-899, Oct. 2003.
DOI
ScienceOn
|
2 |
C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations," Int. Symposium on Low Power Electronics and Design (ISLPED), pp. 116-121, Aug. 2003.
|
3 |
M. W. Kuemerle, S. K. Lichtensteiger, D. W. Douglas, and I. L. Wemple, "Integrated Circuit Design Closure Method for Selective Voltage Binning," U. S. Patent 7475366, Jan. 2009.
|
4 |
V. Zolotov, C. Visweswariah, and J. Xiong, "Voltage Binning Under Process Variation," IEEE/ACM Int. Conf. on Computer-Aided Design Digest of Tech. Paper (ICCAD), pp. 425-432, Nov. 2009.
|
5 |
S. Lichtensteiger, and J. Bickford, "Using Selective Voltage Binning to Maximize Yield," Advanced Semiconductor Manufacturing Conference (ASMC), pp. 7-10, May 2012.
|
6 |
R. Shen, S. X.-D. Tan, and X.-X. Liu, "A New Voltage Binning Technique for Yield Improvement Based on Graph Theory," Int. Symposium on Quality Electronic Design (ISQED), Mar. 2012.
|
7 |
J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE Journal of Solid State Circuits, Vol. 37, No. 11, pp. 1396-1402, Nov. 2002.
DOI
ScienceOn
|
8 |
J. W. Tschanz, S. Narendra, R. Nair, and V. De, "Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors," IEEE Journal of Solid State Circuits, Vol. 38, No. 5, pp. 826-829, May 2003.
DOI
ScienceOn
|