• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.439-442
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• 2004

Timing delays due to VLSI circuit interconnects strongly depend on neighbor line switching patterns as well as input transition time. Considering both the input transition and input switching pattern, a new analytical timing delay model is developed by using the decoupling technique of transfer multi-coupled lines into an effective single line. The analytical timing delay model can determine the timing delay of multi-coupled lines accurately as well as rapidly. It is verified by using DSM-Technology ($0.1{\mu}m$ /low-k copper-based process) that the model has excellent agreement with the results of SPICE simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.352.2-352.2
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• 2014

In this present work, we report a Cu-Mn alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between Mn-based interlayer interlayer, thermal stability was measured with various low-k dielectrics. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the Mn based self-formed barriers after annealing were determined by the C concentration in the dielectric layers.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.51-52
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• 2011

본 연구에서는 전해 구리도금막과 SiN 피복층 사이의 힐락 (Hillock) 및 보이드 (Void) 결함에 미치는 전해 구리도금 공정 및 CVD SiN 피복층 증착 전 NH3 플라즈마 처리 효과에 대해 연구하였다. SiN 피복층 증착전 NH3 플라즈마 효과를 정량화하기 위해 실험계획법을 이용해 NH3 플라즈마 공정 인자가 힐락 결함의 밀도에 미치는 영향에 대해 고찰하였다. 실험결과, 힐락 결함의 밀도는 NH3 플라즈마 인가 시간에 비례한다는 것을 알았다. 보이드 결함의 경우, 구리 씨앗층 및 NH3 플라즈마 조건의 최적화를 통해 구리 씨앗층의 표면 조도를 최소화할 경우 보이드 결함이 최소화된다는 것을 알 수 있었다. 이는 구리 씨앗층의 표면 조도를 최소화함에 따라 전해 구리도금막의 결정립 크기가 커져 결정립 계면에 존재하는 불순물 양이 줄어들었기 때문인 것으로 사료된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.546-546
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• 2008

Copper (Cu) Chemical mechanical polishing (CMP) has been an essential process for Cu wifing of DRAM and NAND flash memory beyond 45nm. Copper has been employed as ideal material for interconnect and metal line due to the low resistivity and high resistant to electro-migration. Damascene process is currently used in conjunction with CMP in the fabrication of multi-level copper interconnects for advanced logic and memory devices. Cu CMP involves removal of material by the combination of chemical and mechanical action. Chemicals in slurry aid in material removal by modifying the surface film while abrasion between the particles, pad, and the modified film facilitates mechanical removal. In our research, we emphasized on the role of chemical effect of slurry on Cu CMP, especially on the effect of amine functional group on removal rate selectivity between Cu and Tantalum-nitride (TaN) film. We investigated the two different kinds of complexing agent both with amine functional group. On the one hand, Polyacrylamide as a polymer affected the stability of abrasive, viscosity of slurry and the corrosion current of copper film especially at high concentration. At higher concentration, the aggregation of abrasive particles was suppressed by the steric effect of PAM, thus showed higher fraction of small particle distribution. It also showed a fluctuation behavior of the viscosity of slurry at high shear rate due to transformation of polymer chain. Also, because of forming thick passivation layer on the surface of Cu film, the diffusion of oxidant to the Cu surface was inhibited; therefore, the corrosion current with 0.7wt% PAM was smaller than that without PAM. the polishing rate of Cu film slightly increased up to 0.3wt%, then decreased with increasing of PAM concentration. On the contrary, the polishing rate of TaN film was strongly suppressed and saturated with increasing of PAM concentration at 0.3wt%. We also studied the electrostatic interaction between abrasive particle and Cu/TaN film with different PAM concentration. On the other hand, amino-methyl-propanol (AMP) as a single molecule does not affect the stability, rheological and corrosion behavior of the slurry as the polymer PAM. The polishing behavior of TaN film and selectivity with AMP appeared the similar trend to the slurry with PAM. The polishing behavior of Cu film with AMP, however, was quite different with that of PAM. We assume this difference was originated from different compactness of surface passivation layer on the Cu film under the same concentration due to the different molecular weight of PAM and AMP.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.29.2-29.2
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• 2009

구리는 낮은 비저항, 높은 열전도도, 우수한 electromigration(EM)저항특성 등을 바탕으로 차세대 nano-scale집적회로의 interconnect application에 적합한 금속재료로서 각광받고 있다. copper interconnect는 damascene process 를주로 이용하는데 CVD를 이용하면 step coverage가우수한 seed layer얻을 수 있어 고집적 소자의 구현이 가능하다. 최근에 비 균등화 반응(disproportionationreaction)을 이용하여 고 순도 구리박막을 제조하기위해 $\beta$-diketonate Cu(I) Lewis-base의 전구체를 많이 이용하는데 그중에서 hexafluoroacetylacetonate(hfac)Cu(I)vinyltrimethylsilane (VTMS)가 널리 이용되고 있다. 그러나 (hfac)Cu(I)(VTMS) 또는 유사계열의 전구체들은 열적안정성및 보관안정성이 부족하여 실제 양산공정에 적합하지 못한 단점이 있었다. 본 연구에 이용된 2가 전구체Cu(dmamb)2는 높은 증기압($70^{\circ}C$, 0.9torr)을 가지며 종래에 주로 이용하던 1가 전구체 (hfac)Cu(VTMS)에 비해 높은 활성화 에너지(~113 kJ/mol)를가짐으로서 열적안정성 및 보관안정성이 우수하다. 다른 한편으로 2가전구체는 안정성이 우수한 만큼 낮은 증기압을 극복하기 위해 리간드에 플루오르를 주로 치환하여 증기압을 높이는데 플루오르는 성장하는 박막의 접착력을약하게 하는 단점을 가진다. 하지만 본 연구에 사용된 Cu(dmamb)2는 리간드에 플루오르를 포함하지 않으며, 따라서 고품질의 박막을 용이한성장환경에서 제조할 수 있는 장점들을 제공한다. 비활성가스 분위기에서 2가전구체는 열에너지에 의해 리간드의 자가환원에따라 금속-리간드 분해가 발생한다. 하지만 수소분위기에서는수소가 환원제로 작용하여 리간드의 분해를 용이하게 하는 특징을 가지며 따라서 비활성분위기일 때 비해 낮은 성장온도를 가진다. 또한 수소는 잔류하는 리간드 및 불순물과 결합하여 휘발성화학종들을 생성하여 고순도의 구리박막제조를 가능하게한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.79-80
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing (CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical planarization/polishing (ECMP) or electro-chemical mechanical planarization was introduced to solve the. technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.409-409
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• 2013

최근, 집적 소자의 미세화에 따라 늘어난 배선 신호 지연 및 상호 간섭, 그리고 소비 전력의 증가는 초고집적 소자 성능 개선에 한계를 가져온다. 이에 따라 기존의 알루미늄(Al)/실리콘 절연 산화막은 구리(Cu)/저유전율 박막(low-k)으로 대체되고 있고, 이는 소자 성능 개선에 큰 영향을 미친다. 그러나 Cu는 Si과 low-k 내부로 확산이 빠르게 일어나 소자의 비저항을 높이고, 누설 전류를 일으키는 등 소자의 성능을 저하시킬 수 있는 문제점을 가지고 있다. 이러한 Cu의 확산을 막기 위하여 Ta, TaN 등과 같은 확산방지막에 대한 연구가 활발히 진행되어 왔으나, 배선 공정의 집적화와 low-k 대체에 따른 공정 및 신뢰성 문제로 인해 새로운 확산방지막의 개발이 필요하게 되었다. 이를 위해, 본 연구에서는 Cu-V 합금을 사용하여 low-k 기판 위에 확산방지막을 자가 형성 시키는 공정에 대한 연구를 진행하였다. 다양한 low-k 기판에서 열처리조건에 따른 Cu-V 합금의 특성을 확인하기 위해 4-point probe를 통한 비저항 평가와 XRD (X-ray diffraction) 분석이 이뤄졌다. 또한, TEM (transmission electron microscope)을 이용하여 $300^{\circ}C$에서 1 시간 동안 열처리를 거쳐 자가형성된 V-based interlayer가 low-k와 Cu의 계면에서 균일하게 형성된 것을 확인하였다. 형성된 V-based interlayer의 barrier 특성을 평가하고자 Cu-V합금/low-k/Si 구조와 Cu/low-k/Si 구조의 leakage current를 비교 분석하였다. Cu/low-k/Si 구조는 비교적 낮은 온도에서 leakage current가 급격히 증가하는 양상을 보였으나, Cu-V 합금/low-k/Si 구조는 $550^{\circ}C$의 thermal stress 에서도 leakage current의 변화가 거의 없었다. 이러한 결과를 바탕으로 열처리를 통해 자가형성된 V-based interlayer의 Cu/low-k 간 확산방지막으로서 가능성을 검증하였다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.