• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.393-404
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• 2016

In this paper, a carrier-based pulse with modulation (PWM) strategy for three-phase three-level inverter is dealt with, which can keep the common mode voltage constant with minimized switching frequency. The voltage gain and the switching frequency in overall operating ranges including overmodulation are investigated and the analytic equations are presented. Finally, the leakage current reduction effect is confirmed by carrying out simulation and experiment. It will be pointed out that the leakage current cannot be perfectly eliminated because of the dead time.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.457-458
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• 2008

This paper presents an output common mode current compensation method to achieve both constant Gm and constant gain. A conventional rail-to-rail CMOS op-amp with constant Gm was designed by using complementary differential input stage and current compensation skills. But it doesn't operate constant gain, because of output resistance variation. With $0.18{\mu}m$ CMOS process, the simulation results show that the differential gain variation can achieve less than 1.3dB. And a 60dB gain, a 13.5MHz unity gain-frequency, and 1mW power consumption, when operating at 1.8V and 10pF load.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1442-1443
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• 2008

본 논문에서는 인쇄회로기판과 도전체 샤시(Chassis)가 연결되었을 때의 복사성 방사(Radiated Emission)의 감소에 대해서 연구하였다. Current Driven 메커니즘 등가회로를 사용하여 전자파 방사의 주요한 원인중 하나인 Common-mode Current를 인쇄회로기판과 Chassis가 연결된 구조에 적용하였다. Chassis의 유무에 따라 복사성 방사의 감소를 확인하고자 2-layer 인쇄회로기판과 SECC(Steel Electro galvanized Cold-rolled Coil) 재질의 Chassis를 나사(Screw)를 통하여 전기적으로 연결하였을 때를 시뮬레이션 하였고, 제작된 구조물을 3m 무반향실에서 복사성 방사를 측정한 후 시뮬레이션과 결과를 비교하였다. 결과로 30MHz$\sim$45MHz에서 최대 10dB 감소의 효과가 있음을 확인하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.1-7
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• 2023

A grid-connected 3-level NPC inverter is a power conversion device that connects renewable energy generators, such as photovoltaic or wind turbines to the grid. Although many studies have focused on this inverter, commercializing it requires strictly satisfying various safety and power quality-related standards. Among many standards, leakage current and grid current total harmonic distortion(THD) can be affected by external factors such as installation environment, aging, and grid conditions. Hence, inverter operations that can satisfy these standards need to be explored. In this study a 3-level NPC inverter operation algorithm using the Phase Opposition Disposition-PWM method that can effectively reduce leakage current and switching frequency adjustment to reduce THD effectively has been proposed.

• Journal of Power Electronics
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• v.19 no.1
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• pp.296-306
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• 2019

The flyback topology is being widely used in power adapters. The coupling capacitance between primary and secondary windings of a flyback transformer is the main path for common-mode (CM) noise conduction. A Y-cap is usually used to effectively suppress EMI noise. However, this results in problems in space, cost, and the danger of safety leakage current. In this paper, the CM noise behaviors due to the electric field coupling of the transformer windings in a flyback adapter with synchronous rectification are analyzed. Then a scheme with balance winding is proposed to reduce the CM noise with a transformer winding design that eliminates the Y-cap. The planar transformer has advantages in terms of its low profile, good heat dissipation and good stray parameter consistency. Based on the proposed scheme, with the help of a full-wave simulation tool, the key parameter influences of the transformer PCB winding design on CM noise are further analyzed. Finally, a PCB transformer for an 18W adapter is designed and tested to verify the effectiveness of the balance winding scheme.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1524-1532
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• 2015

Conventional space vector pulse width modulation based asymmetrical dual inverter configuration produces high common mode voltage (CMV) variations. This CMV causes the flow of common mode current, which adversely affects the motor bearings and electromagnetic interference of nearby electronic systems. In this study, a simple and generalized carrier based pulse width modulation (PWM) technique is proposed for dual inverter configuration. This simple approach generates various continuous and discontinuous modulating signals based PWM algorithms. With the application of the discontinuous modulating signal based PWM algorithm to the asymmetrical dual inverter configuration, the CMV can be reduced with a slightly improved quality of output voltage. The performance of the continuous and discontinuous modulating signals based PWM algorithms is explored through both theoretical and experimental studies. Results show that the discontinuous modulating signal based PWM algorithm efficiently reduces the CMV and switching losses.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.507-515
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• 2004

With the advent of fast power devices, the high dv/dt voltage produced by PWM inverts have been found to cause EMI noise, shaft voltage and bearing current. This paper describes the application of newly developed Conducted EMI reduction SVPWM technique in induction motor drives. The newly developed common mode voltage reduction SVPWM technique don't use any zero-vector states for inverter control, hence it can restrict the common mode voltage more than conventional PWM technique. The validity of the proposed technique by software approach is verified through simulation and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.31-40
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• 2014

This paper describes an optimal configuration for multi-central inverters in a medium-voltage (MV) grid, which is suitable for large-scale photovoltaic (PV) power plants. We theoretically analyze a proposed common-mode equivalent model for problems associated with multi-central transformerless-type three-phase full bridge(3-FB) PV inverters employing two-winding MV transformers. We propose a synchronized PWM control strategy to effectively reduce the common-mode voltages that may simultaneously occur. In addition, we propose that the existing 3-FB topology may also have the configuration of a multi-central inverter with a two-winding MV transformer by making a simple circuit modification. Simulation and experimental results of three 350kW PV inverters in a multi-central configuration verify the effectiveness of the proposed synchronization control strategy. The modified transformerless-type 3-FB topology for a multi-central PV inverter configuration is verified using an experimental prototype of a 100kW PV inverter.

• Journal of Power Electronics
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• v.19 no.1
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• pp.108-118
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• 2019

This paper proposes a DC-link voltage balance controller using the fourth-phase of a three-level neutral-point clamped (NPC) PWM converter with medium vector selection (MVS) PWM for common-mode voltage reduction. MVS PWM makes the voltage reference by synthesizing the voltage vectors that cannot generate common-mode voltage. This PWM method is effective for reducing the EMI noise emitted from converter systems. However, the DC-link voltage imbalance problem is caused by the use of limited voltage vectors. Therefore, in this paper, the effect of MVS PWM on the DC-link voltage of a three-level NPC converter is analyzed. Then a proportional-derivative (PD) controller for the DC-link voltage balance is designed from the DC-link modeling. In addition, feedforward compensation of the neutral point current is included in the proposed PD controller. The effectiveness of the proposed controller is verified by experimental results.

• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.