• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.685-688
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• 2002

In this paper, it is reported that the anode current changes at the constantly applied gate voltages and the current-voltage (I-V) characteristics of Si, Co silicide and Mo silicide field emitter arrays (FEAs) depending on vacuum level from a $10^{-9}$ torr to a $10^{-6}$ torr. The mechanism of the robustness of anode current degradation of Mo silicide FEAs under poor vacuum conditions can be explained by the model of tolerance for the oxygen adsorption and oxidation at the silicide surface. Also, we present the changes of emitting area and work function of the emitters according to vacuum level.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.387-390
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• 1988

The increases in the packing density and the resulting shrinkage of silicon integrated circuit dimensions led to the investigation and successful of the deposited silicide layers as the gate and interconnection and contact metallization. In this paper evaporated Co films on n-Si have been rapid thermal annealed in $N_2$ambient at temperature of $400^{\circ}C-1000^{\circ}C$. The Co silicide formation is characterized by sheet resistance (4PP). Also, silicide growth rate and its reproductivity has been examined by SEM.

• Korean Journal of Materials Research
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• v.14 no.12
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• pp.846-850
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• 2004

NiCo silicide films have been fabricated from $300{\AA}-thick\;Ni_{1-x}Co_{x}(x=0.1\sim0.9)$ on Si-substrates by varying RTA(rapid thermal annealing) temperatures from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 sec. Sheet resistance, cross-sectional microstructure, and chemical composition evolution were measured by a four point probe, a transmission electron microscope(TEM), and an Auger depth profilemeter, respectively. For silicides of the all composition and temperatures except for $80\%$ of the Ni composition, we observed small sheet resistance of sub- $7\;{\Omega}/sq.,$ which was stable even at $1100^{\circ}C$. We report that our newly proposed NiCo silicides may obtain sub 50 nm-thick films by tunning the nickel composition and silicidation temperature. New NiCo silicides from NiCo-alloys may be more appropriate for sub-0.1${\mu}m$ CMOS process, compared to conventional single phase or stacked composit silicides.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.149-154
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• 2005

We fabricated Ni/Co(or Co/Ni) composite silicide layers on the non-patterned wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\~}1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the poly silicon inversion due to fast metal diffusion lead to decrease silicide thickness. Our results imply that we should consider the serious inversion and fast transformation in designing and process f3r the nano-height fully cobalt nickel composite silicide gates.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.215-216
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• 2013

The silicide is a compound of Si with an electropositive component. Silicides are commonly used in silicon-based microelectronics to reduce resistivity of gate and local interconnect metallization. The popular silicide candidates, CoSi2 and TiSi2, have some limitations. TiSi2 showed line width dependent sheet resistance and has difficulty in transformation of the C49 phase to the low resistive C54. CoSi2 consumes more Si than TiSi2. Nickel silicide is a promising material to substitute for those silicide materials providing several advantages; low resistivity, lower Si consumption and lower formation temperature. Nickel silicide (NiSi) nanowire (NW) has features of a geometrically tiny size in terms of diameter and significantly long directional length, with an excellent electrical conductivity. According to these advantages, NiSi NWs have been applied to various nanoscale applications, such as interconnects [1,2], field emitters [3], and functional microscopy tips [4]. Beside its tiny geometric feature, NW can provide a large surface area at a fixed volume. This makes the material viable for photovoltaic architecture, allowing it to be used to enhance the light-active region [5]. Additionally, a recent report has suggested that an effective antireflection coating-layer can be made with by NiSi NW arrays [6]. A unique growth mechanism of nickel silicide (NiSi) nanowires (NWs) was thermodynamically investigated. The reaction between Ni and Si primarily determines NiSi phases according to the deposition condition. Optimum growth conditions were found at $375^{\circ}C$ leading long and high-density NiSi NWs. The ignition of NiSi NWs is determined by the grain size due to the nucleation limited silicide reaction. A successive Ni diffusion through a silicide layer was traced from a NW grown sample. Otherwise Ni-rich or Si-rich phase induces a film type growth. This work demonstrates specific existence of NiSi NW growth [7].

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.18-22
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• 2008

In this paper, the Ni-Co alloy was used for thermal stability estimation comparison with Ni structure. The proposed Ni/Ni-Co structure exhibited wider range of rapid thermal process windows, lower sheet resistance in spite of high temperature annealing up to $700^{\circ}C$ for 30 min, more uniform interface via FE-SEM analysis, NiSi phase peak. Therefore, The proposed Ni/Ni-Co structure is highly promising for highly thermal immune Ni-silicide for nano-scale MOSFET technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.3
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• pp.273-277
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• 2005

We prepared $0.25\~l.5um$ poly silicon gate array test group with $SiO_2$ spacers in order to employ NiCo composite salicide process from 15nm Ni/15nm Co/poly structure. We investigate the residual metal shape evolution by varying the rapid thermal silicide anneal temperature from $700^{\circ}C\;to\;1100^{\circ}C$. We observed the residual metals agglomerated into maze type and line type on $SiO_2$ field and silicide gate, respectively as temperature increased. We propose that lower silicide temperature would be favorable in newly proposed NiCo salicide in order to lessen the agglomeration causing the leakage and scum formation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.195-200
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/70 w-Poly-Si/200 $nm-SiO_2/Si$ and $10nm-Ni_{0.5}Co_{0.5}/70$ nm-Poly-Si/200 $nm-SiO_2/Si$ structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required fur annealing. Silicides underwent rapid anneal at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of the polycrystalline silicon substrate mimicking the gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profile scope were employed for the determination of cross sectional microstructure and thickness. 20nm thick nickel cobalt composite silicides on polycrystalline silicon showed low resistance up to $900^{\circ}C$, while the conventional nickle silicide showed low resistance below $900^{\circ}C$. Through TEM analysis, we confirmed that the 70nm-thick nickel cobalt composite silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. We identified $Ni_3Si_2,\;CoSi_2$ phase at $700^{\circ}C$ using an X-ray diffractometer. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo composite silicide from NiCo alloy films process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.252-258
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• 2013

In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.

• Transactions on Electrical and Electronic Materials
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• v.9 no.4
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• pp.137-142
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• 2008

The parasitic resistance is studied to silicon/metal contact junction for improving device performance and to lower contact/serial resistance silicide in natural sequence. In this paper constructs the stepwise Ni silicide process for parasitic resistance reduction for silicon/metal contact junction. We have investigated multi-step Ni silicide on SiGe substrate with stepwise annealing method as an alternative to compose more thermally reliable Ni silicide layer. Stepwise annealing for silicide formation is exposed to heating environment with $5^{\circ}C/sec$ for 10 seconds and a dwelling for both 10 and 30 seconds, and ramping-up and the dwelling was repeated until the final annealing temperature of $700\;^{\circ}C$ is achieved. Finally a direct comparison for single step and stepwise annealing process is obtained for 20 nm nickel silicide through stepwise annealing is $5.64\;{\Omega}/square$ at $600\;^{\circ}C$, and it is 42 % lower than that of as nickel sputtered. The proposed stepwise annealing for Ni silicidation can provide the least amount of NiSi at the interface of nickel silicide and silicon, and it provides lower resistance, higher thermal-stability, and superior morphology than other thermal treatment.