• Title/Summary/Keyword: Clock generation

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A novel 622Mbps burst mode CDR circuit using two-loop switching

  • Han, Pyung-Su;Lee, Cheon-Oh;Park, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.188-193
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    • 2003
  • This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

Design of a Transponder IC using RF signal (RF signal을 이용한 Transponder IC 설계)

  • 김도균;이광엽
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.911-914
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    • 2000
  • 본 논문에서는 배터리가 없는 ASK 전송방식의 RFID(Radio Frequency IDentification) Transponder 칩 설계에 관한 내용을 다룬다. Transponder IC는 power-generation 회로, clock-generation 회로, digital block, modulator, overoltge protection 회로로 구성된다. 설계된 칩은 저전력 회로를 적용하여 원거리 transponder칩을 구현할 수 있도록 하였다. 설계된 회로는 0.25㎛ 표준 CMOS 공정으로 레이아웃하여 제작하였다.

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Performance Improvement of Anti-collision Algorithm for RFID Protocol and Algorithm Comparison (RFID 프로토콜의 충돌방지 알고리즘의 성능 개선과 알고리즘 비교)

  • Lim, Jung-Hyun;Kim, Ji-Yoon;Jwa, Jeong-Woo;Yang, Doo-Yeong
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.44 no.6
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    • pp.51-61
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    • 2007
  • In this paper, Air-interface protocols of ISO 18000-6 Types and EPCglobal Classes applied to RFID system in UHF band are analyzed, and those anticollision algorithms are realized. Also, the each algorithm which improves the performance of standard protocol is proposed, and the performance is compared when clock period of link timing is a identical condition on $12.5{\mu}s$. As the result, when 500 tags exist simultaneously inside reader interrogation zone, the tag recognition performance of a standard protocol is better in preceding order of Class-1 Generation-1, Type B, Type A, Class-0 and Class-1 Generation-2. And also the performance of improved protocol is better in ascending order of Type B, Type A, Class-1 Generation-1, Class-0 and Class-1 Generation-2. Therefore, performance of tag recognition remarkably depends on the regulated clock period in the protocol and link timing between a reader and a tag.

A proposal of binary sequence generator, Threshold Clock-Controlled LM-128 (클럭 조절 방식의 임계 클럭 조절형 LM-128 이진 수열 발생기 제안)

  • Jo, Jung-bok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.5
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    • pp.1104-1109
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    • 2015
  • Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.

Design of a Multiphase Clock Generator for High Speed Serial Link (고속 시리얼 링크를 위한 다중 위상 클럭 발생기의 설계)

  • 조경선;김수원
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.277-280
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    • 2001
  • The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

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Technological Trend of Optical Frequency Comb Generator (광 주파수 빗 발생기의 기술 동향)

  • Park, Jaegyu;Song, Minje;Han, Sang-Pil;Kim, Sungil;Song, Minhyup
    • Electronics and Telecommunications Trends
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    • v.34 no.5
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    • pp.91-98
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    • 2019
  • Optical frequency comb generators have been investigated as a signal source capable of generating highly stabilized ultrafast pulse lasers. The precise control of the optical frequency comb spacing by RF clock signals has led to a revolutionary paradigm shift in the precise measurement of time and frequency. Optical frequency combs also have advantages such as stable frequency spacing, stable number of lines, and robustness. Owing to these characteristics, optical frequency combs have been applied to the fields of high precision optical clock, communication, spectroscopy, waveform generation, and astronomy. In this article, we introduce the properties (i.e., generation methods, advantages, and so on) of various optical frequency combs, and discuss the expected future technological trends and applications.

A Clock Skew Minimization Technique Considering Temperature Gradient (열 기울기를 고려한 클락 스큐 최소화 기법)

  • Ko, Se-Jin;Lim, Jae-Ho;Kim, Ki-Young;Kim, Seok-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.7
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    • pp.30-36
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    • 2010
  • Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

Distributed Test Method using Logical Clock (Logical Clock을 이용한 분산 시험)

  • Choi, Young-Joon;Kim, Myeong-Chul;Seol, Soon-Uk
    • Journal of KIISE:Computer Systems and Theory
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    • v.28 no.9
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    • pp.469-478
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    • 2001
  • It is difficult to test a distributed system because of the task of controlling concurrent events,. Existing works do not propose the test sequence generation algorithm in a formal way and the amount of message is large due to synchronization. In this paper, we propose a formal test sequence generation algorithm using logical clock to control concurrent events. It can solve the control-observation problem and makes the test results reproducible. It also provides a generic solution such that the algorithm can be used for any possible communication paradigm. In distributed test, the number of channels among the testers increases non-linearly with the number of distributed objects. We propose a new remote test architecture for solving this problem. SDL Tool is used to verify the correctness of the proposed algorithm and it is applied to the message exchange for the establishment of Q.2971 point-to-multipoint call/connection as a case study.

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The King Sejong′s String Clepsydra: (2) Bay and Night Time Announcing System (세종의 자격루 : (2)자격보시장치)

  • 남문현;서문호;한영호
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 1996.11a
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    • pp.702-706
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    • 1996
  • The King Sejong's Striking water-clock was named for its distictive day and night time announcing system. Its time announcing system generates acoustic and visual signals for the twelve double hour, and combinations of two different acoustic signals for the five night watches, The mechanism of this signal generation system is triggered by a copper ball which is mechanically digitized time keeping signal, and is generated from the water clock. The time announcing system consisted four parts: 1) the mechanical amplifier which changes small copper to heavy steel ball, 2) day time announcing system, 3) night time announcing system, 4) sounding mechanism. The time announcing system of King Seong's Striking Clepsidra is remotely related to the Arabic clock system, however, it does have world-widely distictive mechanisms of its era, such as mechanical amplifier, self-weight rachet mechanism, and resetable mechanical computer etc.

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Cell Autonomous Circadian Systems and Their Relation to Inflammation

  • Annamneedi, Venkata Prakash;Park, Jun Woo;Lee, Geum Seon;Kang, Tae Jin
    • Biomolecules & Therapeutics
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    • v.29 no.1
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    • pp.31-40
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    • 2021
  • All living beings on earth have an important mechanism of 24-h periodicity, which controls their physiology, metabolism, and behavior. In humans, 24-h periodicity is regulated by the superchiasmatic nucleus (SCN) through external and environmental cues. Peripheral organs demonstrate circadian rhythms and circadian clock functions, and these are also observed in cultured cell lines. Every cell contains a CLOCK: BMAL1 loop for the generation of circadian rhythms. In this review, we focused on cell autonomous circadian rhythms in immune cells, the inflammatory diseases caused by disruption of circadian rhythms in hormones, and the role of clock genes in inflammatory diseases.