Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2001.06b
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- Pages.277-280
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- 2001
Design of a Multiphase Clock Generator for High Speed Serial Link
고속 시리얼 링크를 위한 다중 위상 클럭 발생기의 설계
Abstract
The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25
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