• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.93-97
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• 2007

In this paper a new clock generation scheme for TDM-CDM converter in the Gap Filler for satellite DMB systems has been proposed. The scheme uses the frame sync signal from the Ku band TDM receiver to lock the VCXO which provides the system clock for the TDM-CDM converter. The locking algorithm can be easily implemented in the FPGA, so that no separate circuitry is needed as in conventional PLL. With a stable OCXO, The scheme can be used to generate the reference clock to the local oscillator for RF parts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.305-315
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• 2007

In this paper, We generated a wander generation model from really measured clock noise data on the transmission node and DOTS in NG-SDH network. and then, We presented the performance of Synch. clock and maximum node level capable network configuration through the clock characteristics simulation on network having the steady-state clock.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.3
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• pp.157-163
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• 2016

Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.

• Journal of IKEEE
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• v.15 no.2
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1633-1640
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• 2006

The problem of reducing power dissipation while simultaneously delivering acceptable levels of performance is becoming a critical concern in high pelf[mann system design. In this paper, we present this power dissipation problem from the clock generation and distribution side. We examine clock power efficiency and several applications as well as wireless communication circuits.