• 센서학회지
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• 제26권6호
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• pp.408-413
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• 2017

In this paper, we newly developed a byte-inverted transmission method for flicker-free visible light communication (VLC). The VLC transmitter sends original data in the former half period of the clock, and inverted data and in the latter half period of the clock. The VLC receiver receives the original data in the in the former half period of the clock. In this system, we used 480Hz clock that was generated from the 60Hz power line. The average optical power of the LED array in the transmitter is constant, thus flicker-free, in the observation time longer than the period of the clock that is about 2ms. This period is shorter than the maximum flickering time period (MFTP) of 5ms that is generally considered to be safe. This configuration is very useful in constructing indoor wireless sensor networks using LED light because it is flicker-free and does not require additional transmission channel for clock transmission.

• 정보처리학회논문지C
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• 제11C권1호
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• pp.123-134
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• 2004

동기 망과 전송망에서의 동기클럭 성능은 망의 안정성 화보와 데이터 전송 보장 측면에서 중요한 요소이다. 그러므로 망을 설계할 때 동기망과 전송망의 동기클럭 성능을 분석하기 위하여 다양한 파라메타를 적용할 수 있고, 그리고 최상상태에서 최악상태까지 망에서 나타날 수 있는 여러 가지 입력레벨을 적용할 수 있는 시뮬레이터가 필요하다. 따라서 본 논문에서는 동기망과 전송망에서의 동기클럭 특성을 분석할 수 있는 SNCA와 TNCA를 개발하였고, 또한 개발된 시뮬레이터를 활용하여 다양한 원더생성, 노드 수, 클럭 상태 등의 입력조건에 따른 NEl, NE2, NE3 등 전송망과 DOTS1과 DOTS2 등 동기 망에서의 동기 클럭 특성과 최대 노드수 결과를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.275-279
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• 2004

A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.899-902
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• 1999

In this paper, we designed a equalizer that moved the multipath of channel in 8-VSB transmission receiver. After doing the initial equalization with "LMS(Least Mean Square)"aigorithm. this equalizer used "Stop-and-Go" algorithm. Because of estimating SER(Symbol to Error Ratio) every a training sequence, this can positively cope with transformation of channel and because of using fast clock than symbol-clock(10.76 MHz), we are able to reduce a multiplier.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.993-996
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• 2007

Depending on applications where transmission bandwidth, wire distance, power consumption and EMI environments vary, design trade-offs must be made to optimize the display interface. After introducing the digital display interface architecture, topics such as cost, EMI, signal integrity, scalability and content protection are discussed with available techniques. Implementation issues are discussed regarding their cost and design complexity. Existing standards are reviewed and comparison on their strengths and shortcomings are discussed.

• ETRI Journal
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• 제30권3호
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.461-463
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• 2018

본 논문에서는 동기식 광 네트워크 SDH(Synchronous Digital Hierarchy)망의 장거리 무선 전송을 위해 필요한 연동 장치를 연구하였다. SDH 방식의 기본 전송단위인 STM-1 신호와 155Mbps급 Synchronous Etherenet의 무선 전송 구현 및 측정 방법을 제안한다. STM-1 전송과 Synchronous Ethernet 전송을 위해 클럭 동기 회복 기능을 제공하며, 안정적인 동기 확보를 위해 예비 클럭 전환 기능을 설계 하였다.

• 한국통신학회논문지
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• 제21권2호
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• pp.417-426
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• 1996

The end-to-end service clock recovery is a critical issue in providing constandt bit rate service through ATM network. The Synchronous Residual Time Stamp(SRTS) algorithm is used to recovery the source clock using time stamp of transmitter. In thispaper, we propose a Differential Residual Time Stamp (DRTS) transmission mechanism to effectively deliver the timing information of source clock in SRTS algorithm. The RTS transmission method simple in its hardware. From the results of field trial of DS3 rate interactive video communication system through B-ISDN testbed, it can be identified that DRTS method is superior to the RTS method.

• 전자공학회논문지S
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• 제35S권12호
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• pp.1-7
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• 1998

본 논문에서는 10Gb/s 클럭/데이터 재생회로의 설계와 제작된 특성에 대해 기술한다. 회로는 알루미나 기판 위에 고속 IC와 초고주파 회로를 이용하여 구현하였다. 주파수와 위상 잠금(frequency and phase locked loop)을 위해 quadri-correlation 방법을 이용하였다. 주파수 잠금 범위는 150MHz 였으며 발생된 rms 지터는 1.0ps 이하였다. 이러한 클럭/데이터 재생회로를 10Gb/s광수신기에 적용하여 동작특성을 확인할 수 있었다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.