1 Gb/s gated-oscillator burst mode CDR for half-rate clock recovery

  • Han, Pyung-Su (High speed information transmission Lab. Yonsei Uinversity) ;
  • Choi, Woo-Young (High speed information transmission Lab. Yonsei University)
  • Published : 2004.12.31

Abstract

A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.

Keywords

References

  1. 'G.984.2 Gigabit-capable passive optical networks (GPON): Physical media dependent(PMD) layer specification', ITU-T, 2003
  2. M. banu and A. E. Dunlop, 'Clock Recovery Circuit with Instantaneous Locking', Electronic letters, Vol. 28, No. 23, pp. 2127 ? 2130, 1992 https://doi.org/10.1049/el:19921366
  3. Chih-Kong Ken Yang and Mark A. Horowitz, 'A 0.8-um CMOS 2.5Gb/s Oversampling Receiver and Transmitter for Serial Links', JSSC, Vol. 31, No. 12, pp. 2015-2023, December 1996 https://doi.org/10.1109/4.545825
  4. Gijung Ahn, Deog-Kyoon Jeong, and Gyudong Kim, 'A 2-Gbaud 0.7-V Swing Voltage-Mode driver and On-Chip Terminator for High-Speed NRZ Data Transmission, JSSC, Vol. 53, No. 6, pp.915-918, June 2000 https://doi.org/10.1109/4.845196