• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1130-1137
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• 2009

This paper proposes a new clock routing design for suppressing clock harmonic effects in a Printed Circuit Board (PCB) for a terrestrial Digital Multimedia Broadcasting(DMB) system. Typical crystal reference frequencies that are widely used in DMB tuners are 16.384 MHz, 19.2 MHz, 24.576 MHz. When the high-order harmonic components of these reference frequencies fall near the RF channel frequencies, receiver sensitivity of the tuners is seriously degraded. In this work, we propose a new clock routing design in order to address the clock harmonic coupling issue. The proposed design incorporates two inductors for isolating the clock ground from the main ground, and adopts a new strip line-style routing instead of the conventional microstrip line style routing to minimize the overlap area with the main ground. As a result, the RF sensitivity of the T-DMB tuner is improved by 2 dB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.73-79
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• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.3
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• pp.128-133
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• 1998

This paper is study on performance analysis of modulator using direct digital frequency synthesizer of Initial Clock Accumulating Method. It has been generally used for PLL or digital frequency synthesizing method to be synthesizd randomly chosen frequency state. In order to improve disadvantage of two methods, we constructed modulator system using DDFS of Initial Clock Accumulating Method. We also confirmed the coherence frequency hopping state and possibility of phase control. The results obtained from the experiments are as follows; First, the synthesized output frequency is proportional to the sampling frequency, according to index, K. Second, the difference of the gain between the basic frequency and the harmonic frequencies was more than 50 [dB], that is, this means facts that is reduced the harmonic frequency factor. Third, coherence frequency hopping state is confirmed by PN code sequence. Here, we confirmed the proposed method cut switching time, this verify facts that is the best characteristic of the frequency hopping. We also verified the fact that the phase varies as the adder is operated set or reset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.12
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• pp.1097-1104
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• 2016

The infrared camera is difficult to satisfy the RE-102 specification of Mil-Std-461. Especially, in the case of UAV electronics, shielded cable is not used, so it is difficult to meet the electromagnetic compatibility standard. In the RE-102 test of the IR camera for UAV, radiated noise exceeding 30 dBuV/m was observed in the range of 50 MHz to 200 MHz. As a result of pcb em scan, peak noise which caused by the harmonic frequency of the digital control signal clock was observed. Radiated noise was reduced by up to 22.9 dBuV/m by applying the spread spectrum clock generator(SSCG) with 3 % down spreading method to the camera control clock.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.