A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector
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Chi, Han-Kyu
(Dep. EE., Seoul National University)
Hwang, Moon-Sang (Dep. EE., Seoul National University) Yoo, Byoung-Joo (Dep. EE., Seoul National University) Choe, Won-Jun (Dep. EE., Seoul National University) Kim, Tae-Ho (Dep. EE., Seoul National University) Moon, Yong-Sam (Dep. EE., Seoul National University) Jeong, Deog-Kyoon (Dep. EE., Seoul National University) |
1 | Actel "Simultaneous Switching Noise and Signal integrity Application Note : AC263" |
2 | Yongsam Moon, "An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance," IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.35, No.3, Mar., 2000. DOI ScienceOn |
3 | Kyoeng-Ho Lee, "Delay locked loop for generating multi-phase clock," Korea Patent, 10-2000-0028609. |
4 | M.-S. Hwang, "Reduction of pump current mismatch in charge-pump PLL," ELECTRONICS LETTERS 29th, Vol.45, No.3, Jan., 2009. |
5 | C. -K. K. Yang "Delay-Locked Loops-an overview," in Phase-Locking in High-Performance Systems From Devices to Architectures, B. Razavi, Ed. NewYork: Wiley/IEEE Press, pp.13-22. |
6 | H.K.Chi, "A 500MHz-to-1.2GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector," International Technical Conference on Circuits/Systems, Computers and Communications, 2010. |
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