1 |
R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All digital PLL and transmitter for mobile phones", IEEE J. Solid-State Circuits, Vol. 40, No. 12, pp. 2469-2482, 2005.
DOI
|
2 |
R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS", IEEE Trans. Circuits Syst. II Express Briefs, Vol. 53, No. 3, pp. 1579-1583, 2006.
|
3 |
R. K. Nandwana, T. Anand, S. Saxena, S.-J. Kim, M. Talegaonkar, A. Elkholy, W.-S. Choi, A. Elshazly, and P. K. Hnumolu, "A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method", IEEE J. Solid-State Circuits, Vol. 50, No. 4, pp. 882-895, 2015.
DOI
|
4 |
M.-S. Chen, Y.-N. Shih, C.-L. Lin, H.-W. Hung, and J. Lee, "A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology", IEEE J. Solid-State Circuits, Vol. 47, No. 3, pp. 627-640, 2012.
DOI
|
5 |
P. K. Hanumolu, V. Kratyuk, G.-Y. Wei, and U.-K. Moon, "A sub-picosecond resolution 0.5-1.5 GHz digital-to-phase converter", IEEE J. Solid-State Circuits, Vol. 43, No. 2, pp.414-424, 2008.
DOI
|
6 |
M.-S. Chen, A. A. Hafez, and C.-K. K. Yang, "A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection", IEEE J. Solid-State Circuits, Vol. 48, No. 11, pp. 2681-2692, 2013.
DOI
|
7 |
A. T. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K. K. Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, "A fractional-N sub-sampling PLL using a pipelined phaseinterpolator with an FoM of-250 dB", IEEE J. Solid-State Circuits, Vol. 51, No. 7, pp. 1630-1640, 2016.
DOI
|
8 |
L. Rodoni, G. Buren, A. Huber, M. Schmatz, and H. Jackel, "A 5.75 to 44 Gb/s quarter rate CDW with data rate selection in 90 nm bulk CMOS", IEEE J. Solid-State Circuits, Vol. 44, No. 7, pp. 1927-1941, 2009.
DOI
|