• Journal of IKEEE
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• v.15 no.1
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• pp.23-28
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• 2011

This paper describes design and implementation of a spread spectrum clock generator(SSCG). The proposed architecture generates the spread spectrum clock controlling a input voltage signal for VCDL(Voltage Controlled Delay Line). Spread charge pump is controlled by the SSC modulation logic block provides a control signal to VCDL through LPF in DLL. By using this architecture, chip area and power consumption can be reduced because it is not necessary additional circuit to control modulation rate. This circuit has been designed and fabricated using the UMC 0.25um CMOS technology. The chip occupies an area of 290${\times}$120um^2.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.538-542
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• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.177-178
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• 2005

Wireless 1394 over IEEE802.15.3 must allow a data reserved for delivery over a wired 1394 network to be delivered over an IEEE802.15.3 wireless network through bridging IEEE 1394 to IEEE802.15.3. Isochronous transfers on the 1394 bus guarantee timely delivery of data. Specifically, isochronous transfers are scheduled by the bus so that they occur once every $125\;{\mu}s$ and require clock time synchronization to complete the real-time data transfer. IEEE1394.1 and Protocol Adaptation Layer for IEEE1394 over IEEE802.15.3 specify clock time synchronization for a wired 1394 bus network to a wired 1394 bus network and wireless 1394 nodes, which are IEEE802.15.3 nodes handling 1394 applications, over IEEE802.15.3. Thus, the clock time synchronizations are just defined within a homogeneous network environment like IEEE1394 or IEEE802.15.3 until now. This paper proposes new clock time synchronization method for wireless 1394 heterogeneous networks between 1394 and 802.15.3. If new method is adopted for various wireless 1394 products, consumer electronics devices such as DTV and Set-top Box or PC devices on a 1394 bus network can transmit real time data to the AV devices on the other 1394 bus in a different place via IEEE 802.15.3.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.4
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• pp.39-46
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has l.04[pF] resolution and can be used as a touch key.

• Progress in Superconductivity
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• v.5 no.1
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• Biomedical Science Letters
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• v.12 no.1
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• pp.53-56
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• 2006

The suprachiasmatic nucleus (SCN) of the anterior hypothalamus is the circadian pacemaker entrained to the 24-hr day by environmental time cues. Major circadian genes such as mPeriod ($mPer1{\sim}3$) and mCryptochrome ($mCry1{\sim}2$) are actively transcribed by the action of CLOCK/BMAL heterodimers, and in turn, these are being suppressed by the mPER/mCRY complex. In the study, the locomotor activity rhythms of mPer1 Knockout (KO) mice are measured, and the expression profiles of Heat Shock Protein 105kDa (HSP 105) genes in the SCN were measured by in situ hybridization. In agreement with previous reports, the locomotor activity rhythm of mPer1 KO mice was much shorter than that of wildtype. In addition, the total bout of activity of mPer1 KO was less in comparison to control mice. The expression of HSP 105 in the SCN of mPer1 KO mice was ranged from CT6 to CT22, with a peak level at CT14, implying that the gene are under the control of circadian clock. However, the expression of HSP 105 in the SCN of wildtype could not be detected in our study. Further analysis will reveal the direct or indirect regulation by mPer1 on the expression in the SCN and the role of the gene in the circadian clock.

• Journal of Advanced Navigation Technology
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• v.13 no.2
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• pp.178-186
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• 2009

SBAS(Satellite Based Augmentation System) provides GNSS satellite orbit and clock corrections for positioning accuracy improvement of GNSS users. In this paper, the accuracy of SBAS satellite orbit and clock corrections were analyzed by comparing with the IGS(International GNSS Service) precise ephemeris. The GPS antenna phase center offsets and the P1-C1 bias are considered for the analysis. The correction data of the US WAAS and the Japanese MSAS were analyzed. The analysis results showed that the SBAS satellite orbit and clock corrections are highly correlated. The correction data accuracy depends on the SBAS ground network size and orbit trajectories.