JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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LDF-CLOCK: The Least-Dirty-First CLOCK Replacement Policy for PCM-based Swap Devices

  • Received : 2014.05.12
  • Accepted : 2014.12.27
  • Published : 2015.02.28
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Abstract

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

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References

  1. M. Qureshi, V. Srinivasan, and J. Rivers, "Scalable high performance main memory system using phase-change memory technology," Proc. IEEE ISCA Conf., pp. 24-33, 2009.
  2. E. Lee, H. Bahn, and S.H. Noh, "Unioning of the buffer cache and journaling layers with non-volatile memory," Proc. USENIX FAST Conf., pp. 73-80, 2013.
  3. S. Lee, H. Bahn, and S. H. Noh, "CLOCK-DWF: a write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures," IEEE Trans. Comput., vol. 63, no. 9, pp. 2187-2200, 2014. https://doi.org/10.1109/TC.2013.98
  4. G. Dhiman, R. Ayoub, and T. Rosing, "PDRAM: a hybrid PRAM and DRAM main memory system," Proc. ACM/IEEE Design Automation Conf., pp.664-559, 2009.
  5. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," Proc. IEEE ISCA Conf., pp.14-23, 2009.
  6. B. Yang, J. Lee, J. Kim, J. Cho, S. Lee, and B. Yu, "A low power phase-change random access memory using a data-comparison write scheme," Proc. IEEE Symp. Circuit and Syst., 2007.
  7. S. Cho and H. Lee, "Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance," Proc. IEEE Symp. Microarchitect., 2009.
  8. B.Wongchaowart, M. Iskander, and S. Cho, "A content-aware block placement algorithm for reducing PRAM storage bit writes," Proc. IEEE MSST Conf., pp.1-11, 2010.
  9. M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Mosse, "Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems," ACM Trans. Architect. Code Optimization, vol. 8, no. 4, 2012.
  10. H. Seok, Y. Park, K. Park, and K. Park, "Efficient page caching algorithm with prediction and migration for a hybrid main memory," Applied Comput. Review, vol. 11, no. 4, 2011.
  11. E. Lee, J. Jang, T. Kim, and H. Bahn, "On-demand snapshot: an efficient versioning file system for phase-change memory," IEEE Trans. Knowledge & Data Engineering, vol. 25, no. 12, pp.2841-2853, 2013. https://doi.org/10.1109/TKDE.2013.35
  12. E. Lee, S. Yoo, J. Jang, and H. Bahn, Shortcut-JFS: a write efficient journaling file system for phase change memory, Proc. IEEE MSST Conf., 2012.
  13. E. Coffman and P. Denning, Operating Systems Theory, Prentice-Hall, pp.241-283, 1973.
  14. R. Carr and J. Hennessy, "WSCLOCK-a simple and effective algorithm for virtual memory management," Proc. ACM SOSP Conf., pp.87-95, 1981.
  15. Valgrind, http://valgrind.org/
  16. B. Nale, R. Ramanujan, M. Swaminathan, and T. Thomas, "Memory channel that supports near memory and far memory access," PCT/US2011/054421, Intel Corporation, 2013.
  17. R. Ramanujan, R. Agarwal, and G. Hinton, "Apparatus and method for implementing a multilevel memory hierarchy having different operating modes," US 20130268728 A1, Intel Corporation, 2013.
  18. PCM product, http://www.micron.com/products/phase-change-memory, Micron, 2013.
  19. R. L. Coulson, "Co-optimizing systems, OS, applications, SSDs and NVM," Proc. Non-Volatile Memories Workshop, 2012.
  20. E. Lee, H. Bahn, S. Yoo, S. H. Noh, "Empirical study of NVM storage: an operating system's perspective and implications," Proc. IEEE MASCOTS Conf., 2014.